CD1284 Datasheet, PDF (51/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

IEEE 1284-Compatible Parallel Interface Controller — CD1284
Following a valid start bit, the bit engine begins receiving data bits. At the end of the programmed
number of bits, following bits are checked for parity (if enabled) and a valid stop bit. A valid stop
bit is defined as a mark or logic ‘1’ on the input. If a valid stop bit is not detected, a framing error is
noted for the character. After a properly assembled (no framing error) character has been received,
it is checked for several special conditions (see Section 5.6 and Section 5.7) and the overrun
condition before it is placed in the receive FIFO. If no errors or special character processing is
required, the character is considered ‘good’ data and placed directly in the FIFO. If errors exist, it is
placed in the FIFO as ‘exception’ data along with status indicating the type of error. As each good
character is placed in the FIFO, the RDCR (Receive Data Count register) is updated to reflect the
number of good characters currently in the FIFO.
The receive FIFO has a programmable threshold to determine the level where the CD1284 requests
receive data service. This level is programmed through the RxTh[3:0] bits (COR3[3:0]). The CPU
can set the threshold to any number of characters from 1 to 12.
Note: This only sets the level where the CD1284 posts a service request and not the depth of the FIFO.
When the CPU responds to a receive good data service request, it can read any number of
characters out of the FIFO, from zero up to the number indicated in the RDCR before exiting the
service routine. If the number read is zero, the CD1284 posts another request for service almost
immediately. If the number of characters read is less than the number indicated by the RDCR, but
enough so that the number in the FIFO falls below the threshold, a new request is not made until
the threshold is once again exceeded. Since the MPU circularly scans the channels, another channel
can post a receive service request before this channel has the opportunity, this is why the request
for service is posted ‘almost immediately’.
5.5.2
Receiver Timer Operations
Also associated with each receiver FIFO is a timer that has its duration set in the RTPR. This timer
provides two services in relation to the receive FIFO operation: a timeout to prevent ‘stale’ data in
the FIFO and a timeout after the last character is removed from the FIFO.
The first type, type 1, occurs if the receive FIFO does not reach the set threshold before the
programmed time period expires. The second type, type 2, occurs if the timer expires and no new
data has been placed in the FIFO after the last character is removed — this is the NNDT (No New
Data Timeout) service request.
The timer is driven by the prescaled clock selected in the PPR in the Global register set. This timer
is loaded with the value contained in the RTPR each time a character is placed in the receive FIFO
or when the last character is removed from the FIFO. Each ‘tick’ of the prescaler decrements the
timer. If the timer reaches zero and the receiver interrupts are enabled, the MPU generates a receive
data service request for the valid timeout condition.
Type 1
If there are characters in the FIFO but the threshold level has not been reached, a good data service
request is posted when the timer expires. This function is provided to prevent data from remaining
in the FIFO for long (potentially infinite) periods of time because the remote did not send enough
data to fill the FIFO to the threshold level. This timeout cannot be disabled.
Datasheet
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