CD1284 Datasheet, PDF (113/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

IEEE 1284-Compatible Parallel Interface Controller — CD1284
Bit
2
1
0
7.1.12
Description
Service Request Modem: ‘1’ indicates request pending.
Service Request Transmit: ‘1’ indicates request pending.
Service Request Receive: ‘1’ indicates request pending.
Transmit Interrupting Channel Register
Register Name: TICR
Register Description: Transmit Interrupting Channel
Access: Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
X
X
X
X
Bit 3
C1
Bit 2
C0
8-Bit Hex Address: 45
Default Value: 00
Bit 1
X
Bit 0
X
See Section 7.1.5 on page 109, the description of the MICR, for details on the TICR.
7.1.13
Transmit Interrupt Register
Register Name: TIR
Register Description: Transmit Interrupt
Access: Read/Write
Bit 7
Bit 6
Bit 5
TxIreq
Txbusy
Txunfair
Bit 4
1
Bit 3
0
Bit 2
0
8-Bit Hex Address: 6A
Default Value: 10
Bit 1
ch[1]
Bit 0
ch[0]
See Section 7.1.6 on page 110, the description of the MIR, for details on the TIR.
7.2
Virtual Registers
The CD1284 has two operational contexts:
Normal: Allows host access to most registers and any channel
Service-acknowledge: Allows host access to some registers specific to the channel requesting
service.
This special set of registers is called Virtual because they are only available to host access and valid
during this service-acknowledge context. At all other times, their contents are undefined and must
not be written to by host software.
The use of Virtual registers and context switching allows the CD1284 to maintain all channel-
specific information. To access the registers pertinent to the channel being serviced, it is not
necessary for the host to make any changes to the device registers.
The service-acknowledge context can be entered in two ways: 1) by activating one of the
SVCACK* input pins (hardware-activated); 2) by the host software when the contents of any one
of TIR, RIR, MIR, or PIR are copied into the CAR during a Poll-mode acknowledge cycle. Chapter
5.0 discusses the differences between these two modes.
Datasheet
113