CD1284 Datasheet, PDF (158/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Table 27. Asynchronous Timing Reference Parameters (Sheet 2 of 2)
Timing
Number
Figure
Parameter
MIN
MAX
Unit
The following timing numbers are for the back-to-back asynchronous DMA timing diagrams.
t₂₅
26 Hold time, DMAACK* active (DMA read/write)
3 CLK
t₂₆
26
Delay, data valid after falling edge DMAACK* (DMA
read)
0.5 CLK + 20
1.5 CLK + 25
ns
t₂₇
26
Hold time, data valid after rising edge DMAACK* (DMA
read)
10
30
ns
26
t₂₈
Inactive time, DMAACK* (DMA read/write)
28
10
ns
t₂₉
26 _{Hold time, DMAREQ* rising edge after}
28 ^{DMAACK* falling edge (DMA read/write)}
10
1 CLK + 15
ns
t₃₀
28 Hold time, DMAACK* active (DMA write)
t₃₁
28
Delay, data valid after falling edge DMAACK* (DMA
write)
2.5 CLK
1.5 CLK
t₃₂
28 Hold time, data valid (DMA write)
3 CLK + 10
ns
NOTES:
1. Timing numbers for RESET* and CLK in the table above are valid for both asynchronous and synchronous specifications.
The device operates on any clock with a 40–60 duty cycle or better.
2. On host-I/O cycles immediately following SVCACK* cycles and writes to EOSRR, DTACK* is delayed by 20 CLKs (1 µs @ 20
MHz, 800 ns @ 25 MHz). On systems that do not use DTACK* to signal the end of the I/O cycle, wait states or some other
form of delay generation must be used to assure that the CD1284 is not accessed until after this time period.
3. As TCLK increases, device performance decreases. A minimum clock frequency of 25 MHz is required to ensure
performance as specified. The recommended maximum TCLK is 1000 ns.
4. DTACK* sources current (drives ‘high’) until the voltage on the DTACK* line is approximately 1.5 V; then DTACK* goes to the
‘open-drain’ (high-impedance) state.
Figure 20. Reset Timing
V_CC
CLK
t_a t_b C2
C1
C2
C1
C2
t₁
RESET*
Note:
For synchronous systems, it is necessary to determine the clock cycle number so that interface
circuitry can stay in lock-step with the device. CLK numbers can be determined if RESET* is
released within the range t_a–t_b; t_a is defined as 10-ns minimum after the rising edge of the clock; t_b
is defined as 5-ns minimum before the next rising edge of the clock. If these conditions are met, the
cycle starting after the second rising edge is C1. See the synchronous timing diagrams for
additional information. Clock numbers are not important in asynchronous systems.
158
Datasheet