CD1284 Datasheet, PDF (135/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

IEEE 1284-Compatible Parallel Interface Controller — CD1284
7.6.8
Serial Service Request Enable Register
Register Name: SRER
Register Description: Serial Service Request Enable
Access: Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
MdmChg
0
0
RxData
Bit 3
0
Bit 2
TxRdy
8-Bit Hex Address: 06
Default Value: 00
Bit 1
TxEmpty
Bit 0
NNDT
This register enables the conditions that cause the CD1284, to post a service request by the SVRR
and the SVCREQ* output pins, and applies to the serial channels only. Each of the individual
enable bits control one type of service request.
Bit
Description
Modem Change: This bit enables the Modem Change service request. When this bit is ‘1’, any selected
7
modem signal change conditions (as programmed by MCOR1 and MCOR2) cause a modem service request
to be posted.
6:5
These bits must always be ‘0’.
Receive Data Enable: This bit enables the posting of receive service requests when characters have been
4
received and either the FIFO reaches the programmed threshold (set by COR3) or the receive timeout period
has expired.
3
This bit must always be ‘0’.
Transmitter Ready and Transmitter Empty: The transmitter can be enabled to post service requests on one
of two conditions: either the FIFO is empty or the Transmitter Shift register is empty.
TxRdy enables the service request on the condition that the FIFO is empty. In this case, there are still two
characters available for transmission before the transmitter underruns (one in the Shift register and one in the
2:1
Holding register).
TxEmpty enables the service request on the condition that the Shift register is empty. The transmitter
underruns due to the latency experienced between the time the service request is posted and the time the
host can load the FIFO. Under normal operating conditions, TxEmpty is set and TxRdy reset when there is no
more data to transmit and the host requires notification that the last character was sent before it can disable
the transmitter.
No New Data Timeout Enable: This bit activates the optional exception service request when all data is
removed from the FIFO and no new data has arrived after a preprogrammed delay period set by the value in
0
the RTPR. The LIVR (or RIVR) indicates a receive exception in the IT2–IT0 vector bits. There is no data
associated with this exception service request. RDSR[7] indicates that the service request is for an NNDT
condition.
7.6.9
Transmit Baud Rate Period Register
Register Name: TBPR
Register Description: Transmit Baud Rate Period
Access: Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Binary Divisor Value
Bit 2
8-Bit Hex Address: 72
Default Value: 41
Bit 1
Bit 0
This register holds the baud rate divisor for the transmitter and is used in conjunction with the
TCOR. This provides the clock, which is divided by this value. The time period produced must
equal the value for one bit time of the transmit data.
Datasheet
135