CD1284 Datasheet, PDF (6/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.5.8 Receive Timeout Period Register......................................................... 133
7.6 Special Character Registers ............................................................................. 133
7.6.1 Special Character Register 1 ............................................................... 133
7.6.2 Special Character Register 2 ............................................................... 133
7.6.3 Special Character Register 3 ............................................................... 134
7.6.4 Special Character Register 4 ............................................................... 134
7.6.5 Received Character Range Detection.................................................. 134
7.6.6 Special Character Range — High ........................................................ 134
7.6.7 Special Character Range — Low ......................................................... 134
7.6.8 Serial Service Request Enable Register .............................................. 135
7.6.9 Transmit Baud Rate Period Register.................................................... 135
7.6.10 Transmit Clock Option Register ........................................................... 136
7.7 Channel Registers — Parallel Pipeline ............................................................. 136
7.7.1 Data Error Register .............................................................................. 136
7.7.2 DMA Buffer Data Register — High....................................................... 137
7.7.3 DMA Buffer Data Register — Low........................................................ 137
7.7.4 Firmware Revision Code Holding Register Status Register................. 138
7.7.5 Local Interrupt Vector Register ............................................................ 138
7.7.6 Parallel Auxiliary Control Register........................................................ 139
7.7.7 Parallel Channel Reset Register .......................................................... 140
7.7.8 Parallel FIFO Control Register ............................................................. 140
7.7.9 Parallel FIFO Empty Pointer Register .................................................. 141
7.7.10 Parallel FIFO Fill Pointer Register........................................................ 142
7.7.11 Parallel FIFO Holding Register 1.......................................................... 142
7.7.12 Parallel FIFO Holding Register 2.......................................................... 142
7.7.13 Parallel FIFO Quantity Register ........................................................... 143
7.7.14 Parallel FIFO Status Register............................................................... 143
7.7.15 Parallel FIFO Threshold Register......................................................... 144
7.7.16 Run Length Count Register.................................................................. 144
7.7.17 Stale Data Timer Count Register ......................................................... 145
7.7.18 Stale Data Timer Period Register......................................................... 145
7.8 Channel Registers — Parallel Port ................................................................... 146
7.8.1 EPP Address Register ......................................................................... 146
7.8.2 Host Timeout Value Register ............................................................... 146
7.8.3 Input Value Register............................................................................. 147
7.8.4 Manual Data Register .......................................................................... 148
7.8.5 Negotiation Enable Register ................................................................ 148
7.8.6 Negotiation Status Register ................................................................. 148
7.8.7 Ones Detect Register ........................................................................... 149
7.8.8 Output Value Register .......................................................................... 150
7.8.9 Parallel Channel Interrupt Enable Register .......................................... 150
7.8.10 Parallel Channel Interrupt Status Register ........................................... 150
7.8.11 Parallel Configuration Register............................................................. 151
7.8.12 Special Command Register.................................................................. 152
7.8.13 Short Pulse Register ............................................................................ 153
7.9 Pin Control Registers ........................................................................................ 154
7.9.1 Signal Status Register.......................................................................... 154
7.9.2 Zeros Detect Register .......................................................................... 154
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