CD1284 Datasheet, PDF (129/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

IEEE 1284-Compatible Parallel Interface Controller — CD1284
7.4.7
LNext Character Register
Register Name: LNC
Register Description: LNext Character
Access: Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
LNext Character
Bit 2
8-Bit Hex Address: 24
Default Value: 00
Bit 1
Bit 0
This register defines the LNext character. If the LNext function is enabled (COR5[6]), the CD1284
examines received characters and compare them against this value. If a match occurs, this character
and the following are placed in the FIFO without any special processing. In effect, the LNext
function causes the CD1284 to ignore characters with special meaning, such as flow-control
characters. There are two exceptions. If the character following the LNext character is either a
break or an error character, LNext is placed in the FIFO, and the following character are treated as
it normally would be for these error conditions.
7.5
7.5.1
Modem Change Option Registers
The CD1284 has two registers that control its response to changes on the modem input pins. It can
be programmed to respond to the low-to-high transition, the high-to-low transition or both. In
addition, the threshold at which the DTR signal is negated can be set by the DTRth3–DTRth0 bits
in MCOR1.
Modem Change Option Register 1
Register Name: MCOR1
Register Description: Modem Change Option Register 1
Access: Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
DSRzd
CTSzd
RIzd
CDzd
Bit 3
DTRth3
Bit 2
DTRth2
8-Bit Hex Address: 15
Default Value: 00
Bit 1
DTRth1
Bit 0
DTRth0
Datasheet
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