CD1284 Datasheet, PDF (49/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

IEEE 1284-Compatible Parallel Interface Controller — CD1284
5.4.2
5.5
The I/O cycle that activates the SVCACKP* input also removes the active SVCREQP* output. The
request output is inactive until after the CPU terminates the acknowledge routine by writing to the
EOSRR. As with the serial channels, this is a dummy operation and the data written is ‘don’t care’.
The purpose of the write is to clear the internal logic of the current request context and allow it to
generate another request when the need arises. Until this write occurs, no further service requests
are made from the parallel channel. When the MPU detects the write to the EOSRR, it zeros-out
the PIVR in preparation for the next service-request cycle.
Software-Activated Context Switch, Parallel
Software-activated acknowledges of the parallel channel differ somewhat from those of the serial
channels. The start of a software acknowledge of the parallel channel is the same as for the serial
channels: the CPU copies the contents of the PIR into the CAR (after first saving the current
contents of the CAR) to set the device context. However, at this point the methods (serial versus
parallel) diverge. The CPU can read either the LIVR or PIVR (or read the status from the two status
registers in the Parallel Port register set) to determine which of the parallel channel blocks is
requesting service, copy the PIR into the CAR (or just load it with ‘x’00’) to set the context, then
proceed to service that request. Once the CPU has satisfied the request needs of the parallel
channel, it must toggle the IntEn bit (PFCR[4]) or clear the PIR. Toggling IntEn clears the PPort
and Pipeline bits and the PPIreq bit (PIR[7]). This action informs the MPU to clean up the PIVR
and remove the external request. The software should then restore the CAR to its previous contents
and exit the service routine.
The PPIreq bit can be cleared at any time by the CPU. If the system design requires the request be
removed quickly, the procedure can be performed at the beginning of the polled service routine. If
the CPU waits until the end of the service routine, it clears the bit itself or terminates the service in
the manner described, letting the MPU do it.
Serial Data Reception and Transmission
The CD1284 has two serial channels, each with a receiver and a transmitter. Although a receiver
and a transmitter pair are associated with each channel, in many respects they operate
independently, sharing only parameter settings regarding character format including length, parity
type if any, and number of stop bits. Each receiver and transmitter has its own baud rate generation
function, allowing a channel to send at one rate and receive at another. Shared and independent
parameters are shown in the following diagram.
RECEIVER
TRANSMITTER
BAUD RATE
BAUD RATE
PARITY
CHARACTER LENGTH
STOP BITS
PRESCALE PERIOD REGISTER
FIFO THRESH
RCV TIMEOUT
Datasheet
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