CD1284 Datasheet, PDF (168/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Figure 32. Synchronous DMA Write Cycle Timing
(Two Back-to-Back 3-Cycle DMA Writes)
DATA SAMPLED
HERE
C
C1
C2
C3
CLK
t₁₅
DMAREQ*
DMAACK*
t₁₈
SEE NOTE
t₁₇
t₂₂
DB[15:0]
VALID
C1
C2
C3
C
DATA SAMPLED
t₁₆
HERE
t₂₅
SEE NOTE
t₁₇
t₂₂
VALID
NOTE: The data is sampled on the second rising edge of CLK following the assertion of DMAACK*, as long as
setup time (t₁₈) is met. If DMAACK* is held active for more than 2.5 CLK cycles, then the next DMA
cycle is simply delayed; the data is still sampled on the second rising CLK edge following the assertion
of DMAACK*.
Figure 33. Synchronous DMA Read Cycle Timing
(Two Back-to-Back 3-Cycle DMA Reads)
C
C1
C2
C3
C1
C2
C3
CLK
DMAREQ*
DMAACK*
DB[15:0]
t₁₅
t₁₈
SEE NOTE
t₁₆
t₂₅
VALID
t₁₈
SEE NOTE
t₂₄
VALID
C
t₂₃
NOTE: The data is driven (t₂₄) after the first falling edge of CLK following the assertion of DMAACK*, as long as setup
time (t₁₈) is met. If DMAACK* is held active for more than 2.5 CLK cycles after C1 falling edge, then the next DMA
cycle is simply delayed, but the data is still driven (t₂₄) after the first falling CLK edge following the next assertion
of DMAACK*.
168
Datasheet