CD1284 Datasheet, PDF (112/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Note: This value does not have any effect on baud rate generation.
The time period generated by this register drives the receive timer and activates the ‘no new data’
and ‘receive data timeout’ interrupts. See the receiver operation discussion in Chapter 5.0 for a
description of receiver timer functions.
7.1.9
Receive Interrupting Channel Register
Register Name: RICR
Register Description: Receive Interrupting Channel
Access: Read/Write
7
6
5
4
X
X
X
X
8-Bit Hex Address: 44
Default Value: 00
3
2
1
0
C1
C0
X
X
See Section 7.1.5 on page 109, the description of the MICR, for details on the RICR.
7.1.10
Receive Interrupt Register
Register Name: RIR
Register Description: Receive Interrupt
Access: Read/Write
Bit 7
Bit 6
Bit 5
RxIreq
Rxbusy
Rxunfair
Bit 4
1
Bit 3
1
Bit 2
0
8-Bit Hex Address: 6B
Default Value: 18
Bit 1
ch[1]
Bit 0
ch[0]
See Section 7.1.6 on page 110, the description of the MIR, for details on the RIR.
7.1.11
Service Request Register
Register Name: SVRR
Register Description: Service Request
Access: Read only
Bit 7
Bit 6
Bit 5
DMAREQ
ExtM
ExtT
Bit 4
ExtR
Bit 3
SRP
Bit 2
SRM
8-Bit Hex Address: 67
Default Value: 00
Bit 1
SRT
Bit 0
SRR
The SVRR reflects the inverse of the state of the service request pins (SVCREQR*, SVCREQT*,
and SVCREQM*). Its primary use is in polled systems, and it allows system software to determine
what, if any, service requests are pending.
Bit
Description
7
DMA Request Status: ‘1’ indicates request pending.
6
ExtM: Reflects the current state of the external SVCREQM* signal.
5
ExtT: Reflects the current state of the external SVCREQT* signal.
4
ExtR: Reflects the current state of the external SVCREQR* signal.
3
Service Request Parallel: ‘1’ indicates request pending.
112
Datasheet