CD1284 Datasheet, PDF (114/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.2.1
Virtual Registers — Serial
Modem Interrupt Status Register
Register Name: MISR
Register Description: Modem Interrupt Status
Access: Read only
Bit 7
Bit 6
Bit 5
DSRch
CTSch
RIch
Bit 4
CDch
Bit 3
0
Bit 2
0
8-Bit Hex Address: 4C
Default Value: 00
Bit 1
0
Bit 0
0
The MISR provides the status regarding a modem service request. If the modem-signal change
detections (zero-to-one or one-to-zero transition) are enabled in MCOR1 or MCOR2, the change
causes a service request and the changed signal is flagged in this register.
Bit
Description
7
Data Set Ready Change: An enabled transition on the Data Set Ready signal causes this bit to be set and a
modem service request posted.
6
Clear To Send Change: An enabled transition on the Clear To Send signal causes this bit to be set and a
modem service request posted.
5
Ring Indicator Change: An enabled transition on the Ring Indicator signal causes this bit to be set and a
modem service request posted.
4
Carrier Detect Change: An enabled transition on the Carrier Detect signal causes this bit to be set and a
modem service request posted.
3:0
These read-only bits always return ‘0’.
7.2.2
Modem Interrupt Vector Register
Register Name: MIVR
Register Description: Modem Interrupt Vector
Access: Read only
Bit 7
Bit 6
Bit 5
X
X
X
Bit 4
X
Bit 3
X
Bit 2
IT2
8-Bit Hex Address: 41
Default Value: 00
Bit 1
IT1
Bit 0
IT0
The value in this register is placed on the data bus, DB[7:0], when SVCACKM* is activated in
response to an active SVCREQM*. See Section 7.4.6 on page 128 for more details on the LIVR.
IT2
IT1
IT0
Description
0
0
0
No modem interrupts.
0
0
1
Group 1: Modem signal change service request.
0
1
0
l
l
l
Invalid.
1
1
1
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Datasheet