CD1284 Datasheet, PDF (157/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

IEEE 1284-Compatible Parallel Interface Controller — CD1284
8.3
AC Characteristics
8.3.1
Asynchronous Timing
Refer to the Figures 6-1 through 6-7 for the reference numbers in the following table.
Table 27. Asynchronous Timing Reference Parameters (Sheet 1 of 2)
Timing
Number
t₁
t₂
t₃
t₄
t₅
t₆
t₇
t₈
t₉
t₁₀
t₁₁
t₁₂
t₁₃
t₁₄
t₁₅
t₁₆
t₁₇
t₁₈
t₁₉
t₂₀
t₂₁
t₂₂
t₂₃
t₂₄
Figure
Parameter
Figure
20
22
22
22
22
22
22
22
22
22
22
23
23
21
21
21
24
24
25
25
27
22
25
25
27
RESET* low pulse width
Address setup time to CS* or DS*
R/W* setup time to CS* or DS*
Address hold time after CS*
R/W* hold time after CS*
DTACK* low to read data valid
DTACK* low from CS* or DS²
Data Bus tristate after CS* or DS* high
CS* or DGRANT* high from DTACK* low
DTACK* inactive from CS* or DGRANT* and DS* high
DS* high pulse width
Write data valid from CS* and DS* low
Write data hold time after DS* high
Clock period (TCLK)^{1, 3}
Clock low time¹
Clock high time¹
Propagation delay, DGRANT* and DS* to DPASS*
Setup time, SVCACK* to DS* and DGRANT*
Setup time, DMAACK* to rising edge of CLK
Hold time, read data after rising edge of CLK
Setup time, write data to rising edge of CLK
DTACK* active pull-up time⁴
Data valid after falling edge of CLK (DMA read)
Hold time, DMAREQ* after DMAACK* falling edge,
last DMA cycle
MIN
10
10
10
0
0
2 T_CLK
0
0
10
0
40.0
0.3 T_CLK
0.3 T_CLK
10
10
10
0
10
MAX
10
4 T_CLK + 30
30
40
1T_CLK
1000
0.7 T_CLK
0.7 T_CLK
35
30
see note 4
25
1 CLK + 15
Unit
T_CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Datasheet
157