CD1284 Datasheet, PDF (164/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Table 28. Synchronous Timing Reference Parameters
Timing
Number
Figure
Parameter
MIN MAX Unit
t₁
29 Setup time, CS* and DS* to C1 rising edge
t₂
29 Setup time, R/W* to C1 rising edge
t₃
29 Setup time, address valid to C1 rising edge
t₄
29 C2 rising edge to data valid
t₅
29 DTACK* low from C3 rising edge¹
t₆
29 CS* and DS* trailing edge to data bus high-impedance
t₇
29 CS* and DS* inactive between host accesses
t₈
29 Hold time, R/W* after C3 rising edge
t₉
29 Hold time, address valid after C3 rising edge
t₁₀
30 Setup time, write data valid to C2 rising edge
t₁₁
31 Setup time, DS* and DGRANT* to C1 rising edge
t₁₂
31 Setup time, SVCACK* to DS* and DGRANT*
t₁₃
30 Hold time, write data valid after C3 rising edge
t₁₄
31 Propagation delay, DS* and DGRANT* to DPASS*
32
t₁₅
Falling edge DMAREQ* after rising edge CLK (DMA write/read)
33
15
ns
15
ns
20
ns
60
ns
30
ns
30
ns
10
ns
20
ns
0
ns
0
ns
30
ns
10
ns
0
ns
35
ns
25
ns
t₁₆
32 _{Hold time, rising edge DMAREQ* after falling edge DMAACK*}
33 ^{(DMA write/read)}
20
ns
t₁₇
32 Setup time, data valid before rising edge C3 (DMA write)
5
ns
32
t₁₈
Setup time, falling edge DMAACK* to falling edge C1 (DMA write/read)
33
10
ns
t₂₁
29 DTACK* active pull-up time²
t₂₂
32 Hold time, data valid after rising edge C3 (DMA write)
5
t₂₃
33 Hold time, data valid after rising edge C1 (DMA read)
10
30
t₂₄
33 Data valid after falling edge C1 (DMA read)
25
t₂₅
33 Inactive time, DMAACK* (DMA read)
10
NOTES:
1. On host I/O cycles immediately following SVCACK* cycles and writes to EOSRR, DTACK* are delayed by 20 CLKs (1 ms @
20 MHz, 800 ns @ 25 MHz). On systems that do not use DTACK* to signal the end of the I/O cycle, wait states or some other
form of delay generation must be used to assure that the CD1284 is not accessed until after this time period.
2. DTACK* sources current (drives ‘high’) until the voltage on the DTACK* line is approximately 1.5 V; then DTACK* enters the
‘open-drain’ (high-impedance) state.
164
Datasheet