CD1284 Datasheet, PDF (116/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Bit
7
6:4
3
2
1
0
7.2.5
provides the character. It is not necessary to read either of these values. If the service acknowledge
is terminated without reading the exception status and data from the RDSR, the internal processor
updates the FIFO pointers as if the status/data were read. The same is true when only the status is
read. Overrun errors are an exception to this (see table below).
Description
Timeout: If the service request enable for timeout is set, this bit indicates that no data has been received
within the receive timeout period set by the RTPR after the last character was removed.
Special Character Detect: These three bits are encoded as follows:
SCDet2
0
0
0
0
1
1
1
1
SCDet1
0
0
1
1
0
0
1
1
SCDet0
0
1
0
1
0
1
0
1
Status
None detected.
Special character 1 matched.
Special character 2 matched.
Special character 3 matched.
Special character 4 matched.
Not used.
End-of-break detected.
Range detect.
NOTE: No special character matching is performed if either a parity (PE) or framing (FE) error occur unless
CMOE is enabled by COR5[5].
Break: Indicates that a break was detected.
Parity Error: Indicates that a character was received with parity other than that programmed in COR1.
Framing Error: Indicates that the character was received with a bad stop bit.
Overrun Error: This bit is set if new data is received, but there is no space available in the FIFO and Holding
register. In this case, the character data is lost, and the overrun flag is applied to the last good data received
before the overrun occurred. Thus, the character read on the subsequent read from the RDSR is good data
and should not be discarded.
Receive Interrupt Vector Register
Register Name: RIVR
Register Description: Receive Interrupt Vector
Access: Read only
Bit 7
Bit 6
Bit 5
X
X
X
Bit 4
X
Bit 3
X
Bit 2
IT2
8-Bit Hex Address: 43
Default Value: 00
Bit 1
IT1
Bit 0
IT0
The value in this register is placed on the data bus, DB[7:0], when SVCACKR* is activated in
response to an active SVCREQR*. See Section 7.4.6 on page 128 for more details on the LIVR.
IT2
IT1
IT0
Description
0
0
0
No receive interrupt active.
0
0
1
Invalid.
0
1
0
116
Datasheet