CD1284 Datasheet, PDF (122/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Bit
Description
7:5
Must be ‘0’.
4
Must be ‘1’.
Select channel enable/disable activity:
XMT EN XMT DIS RCV EN RCV DIS
Encoding
0
0
0
1
Disable receiver.
0
0
1
0
Enable receiver.
0
1
0
0
Disable transmitter.
3:0
1
0
0
0
Enable transmitter.
0
1
0
0
Disable transmitter and receiver.
0
1
1
0
Disable transmitter; enable receiver.
1
0
0
1
Enable transmitter; disable receiver.
1
0
1
0
Enable transmitter and receiver.
7.3.2
Channel Control Status Register
Register Name: CCSR
Register Description: Channel Control Status
Access: Read only
Bit 7
Bit 6
Bit 5
RxEN
RxFloff
RxFlon
Bit 4
0
Bit 3
TxEN
Bit 2
TxFloff
8-Bit Hex Address: 0B
Default Value: 00
Bit 1
TxFlon
Bit 0
0
The CCSR provides current receiver/transmitter status of the selected channel.
Bit
Description
7
Receiver Enabled: This bit is set when the receiver is enabled and cleared when it is disabled.
Receiver Flow Off: This bit indicates that the receiver has requested the remote to stop transmitting through
6
the use of a send XOFF character by a send special character 2 command in the CCR. The bit is cleared
when a send special character 1 (XON) command is issued; the channel is either enabled or disabled, or the
channel is reset.
Receiver Flow On: When a send special character 1 (XON) command is issued by the CCR, this bit is set.
5
This bit is cleared when one of three events has occurred, 1) the first non-flow control character is received,
2) the receiver is either enabled or disabled, 3) or the channel is reset.
4
Reserved: This bit returns ‘0’ when read.
3
Transmitter Enabled: This bit is set when the transmitter is enabled and cleared when it is disabled.
122
Datasheet