CD1284 Datasheet, PDF (162/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Figure 25. Asynchronous DMA Read Cycle Timing
CLK
DMAACK*
t₁₉
‘a’
‘b’
‘c’
MAY CHANGE
t₂₄
DMAREQ*
t₂₃
t₂₀
DB[15:0]
VALID
NOTES:
1. The DMA handshake operates in asynchronous mode only if the AsyncDMA bit is set in PACR.
2. If DMAACK* is released after point ‘a,’ but before point ‘b’ (two rising CLK edges after the falling edge of DMAACK*),
DMB[A1A5:C0]Ki*s),reDleBa[1s5e:d0]aitst₂re₀lefoallsoewdinagt t₂h₀efroislloinwginegdgtheeorfisCinLgK.eIdfgDeMoAf ACCLKK.*IifsDhMelAdApCaKst*tihsishelddgpea, sitt cthoinstreodlsgeth, eit release of
DcoBn[t1r5o:ls0]t;hteheredleaatasebuosf DreBm[1a5in:0s];atchteivedautnatibl uDsMrAemACaiKn*s baecctiovme eusntiinl aDcMtivAeA(CpKoi*nbt e‘cc’)o.mes inactive (point ‘c’).
3. Figure 25 is still valid, however, Figure 26 illustrates more robust timing.
Figure 26. Asynchronous DMA Read Cycle Timing (Two Back-to-Back DMA Reads)
CLK
DMAREQ*
DMAACK* SYNCHRONIZED
HERE
t₂₅
t₂₉
t₂₈
DMAACK*
DB[15:0]
SEE NOTE
t₂₆
t₂₇
VALID
SEE NOTE
VALID
NOTE: The falling edge of DMAACK* is synchronized internally with the rising edge of the clock when asynchronous
timing is selected by PACR[1]. The data valid time can vary by as much as one full CLK cycle depending on when
DMAACK* falling edge occurs in relation to the CLK rising edge. The minimum DMAACK* active time must be met
to ensure that the data has become valid before the rising edge of DMAACK*. The DMAACK* can be extended to
any length, which extends the data valid hold time accordingly. If t₂₅ is not met and DMAACK* is deasserted in less
than t₂₅ (MIN), then the data bus tristates t₂₇ after the third rising clock edge following the assertion of DMAACK*.
162
Datasheet