CD1284 Datasheet, PDF (35/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

IEEE 1284-Compatible Parallel Interface Controller — CD1284
Odd-byte transfers in the reverse direction are handled on an interrupt basis. When the number of
bytes in the FIFO is odd, all bytes, except the last, are transferred by a number of 16-bit DMA
cycles (two bytes per cycle). The odd byte remaining is held in the PFHR1 and an interrupt
generated when the stale data timer expires. Status indicating that PFHR1 has data is shown in the
PFSR. The CPU interrupt service routine must manually remove the remaining byte from the
interface. In the forward direction, an odd remaining byte can be directly written to the PFHR1
once the last DMA cycle is complete.
One additional input signal determines the endian format (whether the least-significant byte is on
data bits 7:0 or 15:8) of the 16-bit DMA buffer. BYTESWAP selects whether the lower or upper
byte of the DMA buffer moves into the FIFO data pipeline first in the forward direction or from the
FIFO data pipeline to the DMA buffer first in the reverse direction. If BYTESWAP is low, the
least-significant byte (DB[7:0]) immediately moves into or out of the data pipeline. If BYTESWAP
is high, the opposite occurs (DB[15:8] move into or out of the pipeline first).
The effective duration of the DMA transfer block (burst) is determined by the threshold value in
the PFTR. Regardless of where the port is moving data, when this threshold is reached (exceeded in
receive; less than in transmit) a DMA cycle begins and remains active until the FIFO has less than
2 bytes remaining (receive) or less than two empty locations remaining (transmit).
The SVRR provides a way to determine if a DMA cycle is being requested. SVRR[7] is true if a
DMA cycle is currently being requested. This status indication is provided as a general system
status.
Refer to Chapter 8.0 for detailed information on DMA cycle options and timing values.
5.3
Serial Port Service Requests
This section describes the service-request structure of the serial ports in the CD1284. Refer to
Section 5.4 for a detailed description of the parallel port service-request architecture.
From the CPU point of view, the CD1284 operates in one of three modes: normal operation,
service request/acknowledge, and DMA. Normal mode allows the CPU to make changes and
obtain current operating status on a global and per-channel basis. Service-request/acknowledge
mode determines when a particular channel requires service, for example, when a serial receive
FIFO has reached its programmed threshold and requires emptying.
A unique behavior of the CD1284 is that a service request can only be responded to after the device
is placed in a service-acknowledge ‘context’. This context switch occurs when the request is
acknowledged, either by activating the appropriate SVCACK* input pin or by proper manipulation
of two internal registers (software-activated mode).
When the MPU detects a condition on a channel that requires CPU attention, it posts a service
request internally and externally. The external request is the activation of one of the SVCREQ*
output pins, depending on whether the type of service needed is for receive, transmit, or modem
signal change. Included with the internal request is a channel pointer to the channel requiring
service. When the service acknowledge begins, this pointer is loaded into the CAR, thus the request
automatically services the proper channel. This is the purpose of the context switch, it prepares the
CD1284 for servicing of the proper channel.
Datasheet
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