CD1284 Datasheet, PDF (78/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Table 20. Signal Names (Sheet 2 of 2)
Names
Compatibility
AkDaRq
PerBsy
PerClk
nDatAv
XFlag
PError
BUSY
ACK*
FAULT*
SELECT
Rev. NB
Rev. BT
Outputs
AkDaRq
PerBsy
PerClk
nDatAv
XFlag
AkDaRq
PerBsy
PerClk
nDatAv
XFlag
ECP
nAkRev
PerAck
PerClk
nPerReq
XFlag
EPP
USER1
nWait
Intr
USER2
USER3
5.12.3
State Machine
The parallel port is controlled by a large synchronous state machine. The state machine is based on
the IEEE STD 1284 specification and conforms to all the functional modes (except extensibility
link options, none of which are currently — as of the print date of this document — defined).
5.12.4
Configuration
At power-up, the interface begins in Compatibility mode (Centronics mode) ready to accept data
from the master. Only the ETxfr bit (PCR[5]) is required to allow transfers in Compatibility mode
(parallel port only; datapath section is separate). PCR[7:5] enable transfers and Negotiation and
Manual modes.
Figure 11. FIFO Data Path Functional Diagram — Receive
(RECEIVE)
PFSR
TAG BIT
TAG BIT
TAG
TAG
TAG (64 BITS)
DB[15:8]
STATUS
STATUS
DB[7:0]
FIFO (64 BYTES)
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Datasheet