CD1284 Datasheet, PDF (119/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

IEEE 1284-Compatible Parallel Interface Controller — CD1284
7.3.1.1
Format 1 — Reset Channel Command
Bit 7
Res Chan
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
FTF
Bit 0
Type
When bit 7 is set, one of three types of reset operations are initiated, based on the value of the least-
significant two bits. Bit 0 sets the type of reset, either channel-only or full-chip, and bit 1 causes the
FIFO of the selected channel to be flushed.
The two types of reset selected by bit 0 cause very different results. When bit 0 is ‘0’, the reset
command effects only the selected channel. Resetting a channel disables both the receiver and
transmitter, and all FIFOs are flushed (cleared). If bit 0 is ‘1’, a full-chip reset is initiated. This reset
has the same results as a hardware reset caused by activation of RESET*: all channels are disabled,
all FIFOs are flushed, and all control registers set to their power-on reset state.
The completion of the reset operation can be detected the same way as though a power-on or
hardware reset had occurred: the GFRCR changes from zero to the value of the firmware revision.
Note that at the start of the reset operation, the GFRCR is cleared, but it can take some time for this
to occur. Host software should wait for the GFRCR to go to zero, and then wait for it to go non-
zero to indicate that the reset operation is complete. The host can clear the GFRCR before issuing
the reset command and then wait for it to become non-zero.
The FTF (flush serial transmit FIFO) command, bit 1, causes the serial transmit FIFO of the
selected channel to be cleared and pointers reset to the empty state. Any data in the FIFO is lost.
Bit
Description
7
This bit must always be ‘1’.
6:2
These bits must always be ‘0’.
These bits are encoded as:
FTF
Type
Function
0
1:0
0
1
1
0
Reset current channel.
1
Full CD1284 reset.
0
Flush serial transmit FIFO of current channel
1
Not used.
7.3.1.2
Bit 7
0
Format 2 — Channel Option Register Change Command
Bit 6
COR Chg
Bit 5
0
Bit 4
0
Bit 3
COR3
Bit 2
COR2
Bit 1
COR1
Bit 0
0
Bit 6 – combined with any bits 3:1 – informs the MPU that a change occurred in one of the Channel
Option registers, COR1, COR2, and/or COR3, respectively. It is permissible to indicate that more
than one COR has changed.
This command exists so that changes in the CORs are noted by the MPU, allowing it to update its
internal working register, since it keeps copies of the CORs in its own shadow registers.
Datasheet
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