CD1284 Datasheet, PDF (32/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Figure 3. CD1284 Functional Block Diagram
PARALLEL
PORT FIFO
PARALLEL
PORT LOGIC
BUS
INTERFACE
AND DMA
LOGIC
INTERRUPT
LOGIC
MPU
ROM
CONTROL STATE
MACHINE
RAM
CHANNEL 2
LOGIC AND BIT
TIMING
CHANNEL 3
LOGIC AND BIT
TIMING
Figure 4. Internal Address Generation
CPU
ADDRESS
ADDRESS
GENERATION
RAM REGISTER
ARRAY
PARALLEL PORT
REGISTERS
(CHANNEL 0)
CHANNEL 2 REGISTERS
CAR
CHANNEL 3 REGISTERS
The serial data channels are made of ‘bit engines’ that off-load the task of receiving and
transmitting each bit from the MPU. When receiving data and after processing a complete bit, the
bit engines interrupt the MPU so that it can perform the next required task. For example, the MPU
takes the bit and adds it to a character being assembled. When transmitting, it sends the bit engine
the next bit of the character being transmitted. The MPU is not concerned with basic bit timing; this
task is handled by the bit engines, leaving the MPU free to perform higher-level processing, such as
detecting special characters.
32
Datasheet