CD1284 Datasheet, PDF (148/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.8.4
Manual Data Register
Register Name: MDR
Register Description: Manual Data
Access: Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
8-bit Binary Data
Bit 2
8-Bit Hex Address: 21
Default Value: 00
Bit 1
Bit 0
This read/write register can read the state of the PD[7:0] signals in any mode. If the ManMd bit
(PCR[7]) and the MMDir and ManOE bits (PCR[1:0]) are set, then the value written into this
register is driven onto the PD[7:0] signals.
7.8.5
Negotiation Enable Register
Register Name: NER
Register Description: Negotiation Enable
Access: Read/Write
Bit 7
Bit 6
Bit 5
0
RID
0
Bit 4
EPP
Bit 3
RLE
Bit 2
ECP
8-Bit Hex Address: 28
Default Value: 00
Bit 1
RVB
Bit 0
RVN
Each bit set along with EICR (PCR[6]) allows the CD1284 to engage in IEEE STD 1284
negotiations and move into the corresponding protocol. It is assumed that the peripheral host
software responds to a request for slave ID and is able to send an ID string in any supported
protocol. In response to an ID request, the CD1284 does not provide a method of storing and
automatically sending an ID string. Note that the EPP protocol does not have provision for slave ID
requests.
Bit
Description
7
Reserved: This read-only bit is always ‘0’.
6
Request Slave ID
5
Reserved: This bit must always be ‘0’.
4
EPP Mode Enable
3
Run Length Encoding in ECP Mode Enable
2
ECP Mode Enable
1
Reverse Byte Mode Enable
0
Reverse Nibble Mode Enable
7.8.6
Negotiation Status Register
Register Name: NSR
Register Description: Negotiation Status
Access: Read/Write
Bit 7
Bit 6
Bit 5
NegOK
NegFl
HostTO
Bit 4
ImedTerm
Bit 3
8-Bit Hex Address: 29
Default Value: 00
Bit 2
Bit 1
4-bit Negotiation Result Code
Bit 0
The results of negotiation attempts are stored in this register.
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Datasheet