CD1284 Datasheet, PDF (12/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
1.0
Overview
Ideal for printers, scanners, tape drives, set-top boxes, and data acquisition applications, the
CD1284 is a multi-function interface controller that implements a high-speed, multi-protocol
parallel port and two asynchronous serial ports. The device has both programmed I/O and DMA
operation (parallel port only), providing flexibility in local CPU interface design and high-speed
data transfers between the device and main memory.
The parallel port implements all modes of the IEEE STD 1284 Standard Signaling Method for
Bidirectional Parallel Peripheral Interface for Personal Computers specification, including EPP,
ECP, Reverse Byte, Reverse Nibble, and Compatible. Data transfer rates (up to 2 Mbytes/sec.) are
achievable on the parallel port when the device operates with a 25-MHz clock. The parallel port
data and control signals implement the IEEE STD 1284-defined Level-2 interface in drive type
(symmetrical), current capability (±14 mA), slew rate (0.4 V/ns), and 0.8 V hysteresis ( 2.0 V to
+7.0 V protection is not implemented).
The two serial ports implement the standard asynchronous protocol. Functionally, the serial ports
are identical and register-set-compatible with the CD1400. The table below, shows the differences
between the CD1283 and CD1284.
Device
CD1283
CD1284
Number of
Serial Channels
0
2
Number of
Parallel Channels
1
1
Also included is a general-purpose port that provides eight bits of individual direction
programmable I/O that can be used for status and control of external functions.
Theory of Operation
The CD1284 is an efficient high-performance communications controller using an on-chip RISC
processor, which off-loads much of the work of sending and receiving data from the CPU.
Specifically for data communications applications, the RISC processor employs a high-
performance architecture developed by Intel. This internal CPU executes all instructions in one
clock cycle, and uses a windowed architecture to ensure zero-overhead context switching for each
type of internal interrupt. The processor is transparent to the user and does not require any
programming. It manages all serial data movement between the CPU and the two serial channels
and provides a flexible interrupt interface for the parallel channel. The parallel channel, being
separate and having its own intelligence, implements a very high-speed, peripheral-side parallel
data interface.
Each of the serial channels consist of separate 12- byte receive and transmit FIFOs. The parallel
channel has a single 64-byte FIFO to support the higher speeds obtainable on the parallel data port.
The serial receive FIFOs all have programmable thresholds to minimize interrupt latency
requirements. The parallel port FIFO has a programmable DMA threshold in both the receive and
transmit directions. The deep FIFOs reduce both the number of interrupt requests made of the CPU
and the time required to service them. The time required to service the requests is reduced by four
unique vectors that provide internal interrupt conditions. Whether it is receive, transmit, modem
signal change, or parallel port, the system spends less time determining the source of the
interrupt.The serial receive interrupt service time is further reduced by providing two types of
receive vectors: one for ‘good’ data and the other for ‘exception’ data. The CPU does not spend
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Datasheet