CD1284 Datasheet, PDF (48/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
5.4.1
A direction change (DirCh) interrupt occurs when the remote master has reversed the interface
from ECP forward to ECP reverse or ECP reverse to ECP forward. The IDReq interrupt is
generated when the remote master issues an ID Request command during IEEE 1284 negotiations.
The normal response by the local CPU is to send its ID string after reversing the direction of the
data pipeline by setting the DMAdir bit to ‘1’.
In an interrupt-driven system, as with the serial channel requests, the SVCREQP* output normally
connects to one of the local CPU interrupt control inputs. It can also be OR’ed together, through an
external gate, with the serial request outputs to produce a single interrupt request to the local CPU.
The interrupt service routine scans the SVRR and determines the actual source of the interrupt.
The parallel channel has the same Vector register arrangement as the serial channels. The LIVR
must be initialized by the local CPU in the same manner as the serial channels; the upper five bits
are defined by the local CPU and can be any value appropriate to the system design. The lower
three bits should be initialized to zero during the programming of the LIVR, however they are
‘don’t cares’ and masked in the PIVR to provide the vector indicating the source and type of
request from the parallel channel.
Access to the parallel channel LIVR is made by first setting the CAR to ‘x’00’, making the
Channel Zero register set accessible. Since the LIVR is a read/write register, the local CPU can
read it at any time. When read during a normal read cycle, it returns the original value written to it.
When a service acknowledge is performed, the upper five bits of LIVR are copied into PIVR.
The encoding of the three least-significant bits of PIVR during a service acknowledge cycle
indicates which of the functional blocks in the parallel channel is requesting service and is as
follows:
IT2
(Bit 2)
1
1
1
IT1
(Bit 1)
0
0
1
IT0
(Bit 0)
0
1
0
Requestor
Channel control state machine
Data pipeline
Both
The encoding of the parallel channel service-request status was designed using the remaining
unused states of the CD1400: ‘100’, ‘101’, and ‘110’. The other states of these three bits are
already used to indicate serial interrupt status in RIVR, TIVR, and MIVR.
Hardware-Activated Context Switch, Parallel
When conditions within the parallel channel require attention, a request is made by the
SVCREQP* output. If the system is interrupt driven, this output would be connected to the CPU
interrupt generation circuitry. In a hardware-activated service-acknowledge system, the CPU
responds to the request by activating the SVCACKP* input (along with DGRANT* and DS*) in
the same manner as the serial channels; the CS* input is not used and must remain inactive (high).
The CD1284 responds to the SVCACKP* cycle by driving the contents of the PIVR onto the data
bus with IT2–IT0 encoded as shown above. The SVCACK cycle also places the device in the
correct context to service the parallel channel request.
The vector supplied by the PIVR indicates which block of the parallel channel requested service;
the cause of the request is indicated in the Request Status registers of each: the PCISR in the
channel control state-machine block and/or the PFSR in the data pipeline block. Refer to Chapter
7.0 for detailed descriptions of the various status bits in these registers.
48
Datasheet