CD1284 Datasheet, PDF (100/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Figure 19. Polling Flow Chart
POLL DEVICE AGAIN
HARDWARE RESET
SOFTWARE RESET
INITIALIZE DEVICE
NOTE: It may not be necessary to poll the PFSR if
DMA requests are enabled. With DMA
requests enabled, the DMAREQ bit
(SVRR[7]) can be polled to determine
when a FIFO threshold is exceeded. If
DMA requests are disabled, the PFSR
must be polled to determine when to move
data to and from the FIFO. If DMA requests
are enabled, data must be read through the
DMABUF register; this requires a 16-bit
data bus.
POLL DEVICE AGAIN
DMAREQ
SET
SERVICE DMA REQUEST
CHANGE DIRECTION
RETURN ID TO HOST
RESET PRINTER
DirCh
IDReq
nInit
TEST
SVRR
SRP SET
= _00H
TEST
PIR
Pipeline SET
PPort SET
TEST
PCISR
SigCh
TEST
SSR
NegCh SET
TEST
NSR
= 00H
TEST
PFSR
DataErr
FF FULL (receiving)
OR
EMPTY (transmiting)
HR DATA
OR
HR TAG
TEST
HRSR
TEST
PFSR
SERVICE NEGOTIATION
CHANGE
SERVICE
SIGNAL
CHANGE
INTERRUPT
SERVICE
ERROR
INTERRUPT
SERVICE
APPROPRIATE
HOLDING
REGISTER
SERVICE
FIFO
6.5.1
Software-Activated Service Examples (Poll)
The scanning loop for Poll-mode operation is shown in Section 6.3. Software activation of the
context switch is performed in the same manner, but termination of the service is done in two ways.
The first method is similar to the serial channel method and the second method can work well in
certain systems, but requires extra steps.
The first method follows the same basic procedure as the serial channels, but the termination
sequence requires only that the upper bit (PPIreq) of the PIR is cleared by the CPU. Since Fair
Share is not implemented on the parallel channel, there is no ‘unfair’ bit in the PIR; the ‘busy’
status is maintained by the MPU differently and is not maintained in the PIR.
100
Datasheet