CD1284 Datasheet, PDF (140/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Bit
2
1
0
7.7.7
Description
Reserved: Must be ‘0.’
AsyncDMA: AsyncDMA causes the device to synchronize the DMAACK* signal to the internal clock (rising
clock edge). This capability provides an asynchronous DMA interface for systems that cannot meet the set-up
times required by the synchronous DMA logic.
Refer to Chapter 8.0 for specific timing relationships between CLK and DMAACK* when AsyncDMA is
enabled.
Unfair: This bit overrides the Fair Share function of the device. If this bit is set, the device posts service
requests even if the service request is already asserted by an external device. The override is in effect for
channels 2 and 3; Fair Share is not functional on the parallel service request.
For applications where the three serial channel service request outputs are wire-OR’ed together, set Unfair so
that an interrupt of one type does not prevent posting one of the other types (receive, transmit, and modem).
Parallel Channel Reset Register
Register Name: PCRR
Register Description: Parallel Channel Reset
Access: Read/Write
Bit 7
Bit 6
Bit 5
0
0
0
Bit 4
0
Bit 3
0
Bit 2
0
8-Bit Hex Address: 6C
Default Value: 00
Bit 1
0
Bit 0
PChReset
This register exists only in the Channel 0 register set and is in the equivalent address location as the
MSVR register of the serial channels.
Bit
Description
7:1
Reserved: Must be ‘0’
PChReset: Setting this bit asserts the equivalent of a hardware power-on reset to the parallel channel,
0
channel 0. If set by the host, it must be cleared to resume normal parallel channel operation. This hardware
reset affects only the parallel channel and has no affect on other functions of the device.
7.7.8
Parallel FIFO Control Register
Register Name: PFCR
Register Description: Parallel FIFO Control
Access: Read/Write
Bit 7
Bit 6
Bit 5
FIFOres
DMAen
DMAdir
Bit 4
IntEn
Bit 3
RLEen
Bit 2
setTAG
8-Bit Hex Address: 31
Default Value: 00
Bit 1
ErrEn
Bit 0
DMAbufWe
This register controls overall function of the parallel FIFO. These functions include resetting
(flushing) the FIFO, enabling DMA transfers, enabling host interrupts, run-length encoding, and so
on. The host sets these bits according to the mode of operation required.
After hard reset (RESET* or a CCR command of x’81 in one of the two serial channels), this
register is cleared to all zeros.
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Datasheet