CD1284 Datasheet, PDF (31/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

5.0
5.1
IEEE 1284-Compatible Parallel Interface Controller — CD1284
Functional Description
Device Architecture
The CD1284 can be described as a small computer system designed for the purpose of sending and
receiving both serial and parallel data. It comprises a RISC processor (Multi-Channel Processing
Unit or MPU), RAM, ROM, local CPU bus interface logic, two serial data channels, and one IEEE
1284-compliant parallel port with a specialized data pipeline designed for high-speed transfers.
Architecturally, the CD1284 is two devices merged into a single unit. One part is a modified, two-
channel version of the Intel CD1400. The other part is a specialized parallel interface port
supported by its own deep FIFO and DMA interface logic. The interrupt structure of the CD1400
has been enhanced to include the interrupt requirements of the parallel port. This section describes
the modified CD1400 core and overall device architecture. Further sections provide details specific
to the parallel channel. Chapter 7.0 provides detailed bit descriptions and encoding for the registers
discussed in this chapter.
The MPU is a true RISC processor. In addition to having compact and efficient instructions, the
MPU has a ‘windowed’ architecture that allows it to handle one channel and its registers at a time.
Before beginning operations on a given channel, it loads an internal Index register that forces all
accesses to the appropriate set of registers. The Index register becomes part of the internal address
and allows direct addressing of the register bank and all hardware resources of the selected
channel. No address computation is required to select the proper channel.
This same windowed scheme is carried through to the CPU interface as well (Figure 4). For all
channel-specific accesses, the CPU first loads the CAR (Channel Access register) with a pointer to
the channel to be accessed. Thereafter, all read and write operations occur with the proper channel.
The software defines the register address once and this is valid for all channels because the CAR is
part of the internal addressing.
Datasheet
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