CD1284 Datasheet, PDF (20/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Pin Name
RXD3
TXD2
RXD2
RTS2*
RTS3*
DTR2*
DTR3*
CTS2*
CTS3*
DSR2*
DSR3*
CD2*
CD3*
RI2*
RI3*
N/C
Type
Number
of Pins
Pin
Number
(Sheet 3 of 3)
I
1
17
O
1
18
I
1
19
O
1
26
O
1
21
O
1
25
O
1
20
I
1
27
I
1
22
I
1
28
I
1
23
I
1
29
I
1
24
I
1
15
I
1
14
–
1
74
Reset
State
High
High
High
High
High
Table 1. Pin Descriptions (Sheet 1 of 4)
Symbol
Pin No.
Type
Description
RESET*
OUTEN
CLK
CLK/2
DB[15:0]
A[6:0]
R/W*
CS*
ACTIVE-LOW RESET: This input initializes the device to the default condition. All
79
I
internal registers are set to their reset condition and all transfer operations are set to
the default state.
OUTPUT ENABLE: This pin must be ‘1’ to enable output pin functions. When OUTEN
83
I
is ‘0’, it forces all output pins to remain in a tristate condition. Typically, OUTEN is used
only for test purposes. User designs must tie this pin to V_CC through a pull-up resistor.
73
I
SYSTEM CLOCK: This input has a 25-MHz maximum; 16 MHz is the recommended
minimum for satisfactory device performance.
80
O
SYSTEM CLOCK DIVIDED BY TWO OUTPUT: This signal is equivalent to the
internal operating clock of the device.
BIDIRECTIONAL DATA BUS: Only DMA transfers and writes to the DMA Buffer
92–99, 2–9
I/O
register are true 16-bit operations. During all register writes other than to the DMA
Buffer register, bits [7:0] are written to the addressed register. Register reads duplicate
the register contents on both the lower byte [7:0] and upper byte [15:8].
84–90
ADDRESS BUS: Together with CS* or one of the SVCACK* inputs and DS*, this input
I
selects an On-Chip register for a read or write operation or an acknowledgment to an
service request.
76
I
READ/WRITE*: This input must be ‘1’ for a register read operation, and must be ‘0’ for
a register write. R/W* is ignored for DMA operations.
ACTIVE-LOW CHIP SELECT: When active, the input CS* combines with DS*,
78
I
initiates an I/O cycle with the CD1284. CS* must be ‘1’ during DMA read/write
operations.
20
Datasheet