CD1284 Datasheet, PDF (22/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Table 1. Pin Descriptions (Sheet 3 of 4)
Symbol
Pin No.
Type
Description
DPASS*
ACTIVE-LOW DAISY PASS: This output is driven active during service acknowledge
cycles to enable the next device in the daisy chain. It is driven active when no valid
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service request exists for the type of service acknowledge input active. In multiple
CD1284 designs, this signal is normally connected to the DGRANT* input of the next
device in the chain.
PD[7:0]
41–48
PARALLEL PORT DATA LINES [7:0]: Bidirectional (depending on the protocol being
I/O used), these signals are used to transfer data through the interface between the
master and slave.
GP[7:0]
53–60
GENERAL PURPOSE I/O [7:0]: General-purpose input/output port data lines. These
I/O
signals are individually direction programmable and act as inputs or outputs. The
corresponding bit in the GPDIR register controls the direction of each signal. The
GPIO register provides the control/status of the actual signals.
A_1284
31
I
1284 ACTIVE INPUT: (SLCTIN* in Compatibility mode). Active-high.
nInit
34
I
INIT SIGNAL: (INIT* in Compatibility mode). Active-low.
HstBsy
32
I
HOST BUSY: (AUTOFD* in Compatibility mode). Active-high.
HstClk
33
I
HOST CLOCK: (STROBE* in Compatibility mode). Active-low.
The above four parallel handshake signals are driven by the master in an IEEE STD 1284 interface, and as such are inputs to
the CD1284. Their functions depend on the transfer protocol selected. Refer to the IEEE STD 1284 document for protocol
functions.
PerClk
37
O
PERIPHERAL CLOCK: (ACK* in Compatibility mode). Active-low.
PerBsy
36
O
PERIPHERAL BUSY: (BUSY in Compatibility mode). Active-high.
AkDaRq
35
O
ACKNOWLEDGE DATA REQUEST: (PError in Compatibility mode).
Xflag
39
O
EXTENSIBILITY FLAG: (SELECT in Compatibility mode).
nDatAv
38
O
DATA AVAILABLE: (FAULT* in Compatibility mode). Active-low.
The above five parallel handshake signals are driven by the slave in an IEEE STD 1284 interface and are outputs from the
CD1284. Their functions depend on the transfer protocol selected. Refer to the IEEE STD 1284 document for protocol functions.
EBDIR
EXTERNAL BUFFER DIRECTION: This signal is controlled by the internal parallel-
port-control state machine and is used to control the direction of an external buffer
connected to the parallel-port data bus. An external buffer could be desirable in
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applications that require higher drive capacity than those provided by the CD1284.
EBDIR can be used in conjunction with PDBEN to control this buffer. EBDIR is a logic
‘0’ when the parallel data bus is in an output mode and a logic ‘1’ when in an input
mode. It can be connected directly to the direction control input of a 74245-type
device.
PDBEN
PARALLEL DATA BUS ENABLE: This signal can be used to control a buffer on the
parallel port data lines in applications requiring more signal drive capability than that
provided by the CD1284. The signal is controlled by the internal parallel port control
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state-machine. When low, the parallel port data bus is off (not driving); when high, the
port is in an output mode and is actively driving. The signal toggles between on and off
states during output modes and is active (high) only when the data bus pins are in the
active driving state. This signal can be logically connected to the enable control of
74245 (or equivalent) bidirectional buffers.
TXD[3,2]
16, 18
O
TRANSMIT DATA: TXD[3,2] are outputs of serial channel numbers two and three.
RXD[3,2]
17, 19
I
RECEIVE DATA: RXD[3, 2] are outputs of serial channel numbers two and three.
RTS[3,2]*
21, 26
O
REQUEST TO SEND: These are active-low outputs of serial channel numbers two
and three.
DTR[3,2]*
20, 25
O
DATA TERMINAL READY: These are active-low outputs of serial channels two and
three.
CTS[3,2]*
22, 27
I
CLEAR TO SEND: These are active-low inputs for serial channels two and three.
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