CD1284 Datasheet, PDF (79/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

IEEE 1284-Compatible Parallel Interface Controller — CD1284
5.12.5
5.12.6
5.12.7
Interrupts
Interrupts are enabled in the PCIER and interrupt status can be read in the PCISR. These two
registers have the same format.
Manual Mode
Manual mode allows direct control of the five output control signals and the PD bus. It is not
intended for data transfers, but rather for advanced diagnostics. Enter Manual mode by setting the
ManMd bit (PCR[7]) when the interface is in Compatibility mode.
The MMDir bit (PCR[1]) sets the direction of the PD bus: 0 = input; 1 = output. When the MMDir
bit is set to ‘1’, data for the PD bus comes from the MDR. The ManOE bit controls the tristate
buffer on the PD bus: 0 = floating; 1 = driving. When MMDir is ‘0’, ManOE is ignored, PD[7:0]
are inputs, and the data can be read in the MDR.
Control Signals
Output signals are controlled by the OVR. The degree of control depends on the current mode. In
Manual mode, all five signals are under user control. In Compatible and EPP modes, only three
signals are available; the others are set by the state machine.
IVR, ZDR, ODR, and SSR monitor the four input signals. These four registers have a common
format. The IVR always shows the values of the four input pins. The ZDR and ODR allow the user
to force interrupts on specific signal transitions. Bits set in ZDR generate an interrupt if the
specified signal changes from ‘1’ to ‘0’. Similarly, bits set in ODR cause an interrupt if the
specified signal changes from ‘0’ to ‘1’. Setting both bits generates interrupts on either transition.
The SSR shows the status of signal changes according to ZDR and ODR. SSR indicates which
signal changed. (It is necessary for the user to read IVR to determine how the signal changed.) The
signal change interrupt is enabled with the SigCh bit (PCIER[4]).
Datasheet
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