CD1284 Datasheet, PDF (154/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
slow masters that require an ACK* pulse longer than the maximum specified in the IEEE STD
1284 specification. The table below shows some examples of the necessary binary value for
various system clock frequencies to set the 500-ns pulse width.
Clock
(MHz)
16
20
25
SPR Value
8
10
13
Resultant Pulse Width
(ns)
500
500
520
7.9
7.9.1
Pin Control Registers
The parallel port has five outputs and four inputs. The pin assignments are the same as those
defined in the IEEE STD 1284 specification. The definition of the pins depends on the current
negotiated mode; these are detailed in the following descriptions.
Signal Status Register
Register Name: SSR
Register Description: Signal Status
Access: Read/Write
Bit 7
Bit 6
Bit 5
0
0
0
Bit 4
0
Bit 3
A1284
Bit 2
nInit
8-Bit Hex Address: 2F
Default Value: 00
Bit 1
HstBsy
Bit 0
HstClk
The bits in this register show the results of changes specified in the ODR and ZDR. Normally, the
host reads this register in response to a signal change interrupt generated by the CD1284. This
register is active and valid only in Manual mode. Bits 7:4 return zeros when read. A write of any
value to the register clears it.
7.9.2
Zeros Detect Register
Register Name: ZDR
Register Description: Zeros Detect
Access: Read/Write
0
0
0
8-Bit Hex Address: 2C
Default Value: 00
0
A1284
nInit
HstBsy
HstClk
Setting the bits in this register enables the CD1284 to generate an interrupt – if the SigCh bit
(PCIER[4]) is set – when the selected signal changes from high-to-low (falling edge). Bits 7:4 are
reserved and must be written as ‘0’; they return ‘0’ when read. The settings in this register have no
effect (that is, the SigCh interrupt is not generated) unless the device is in Manual mode.
154
Datasheet