CD1284 Datasheet, PDF (13/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

IEEE 1284-Compatible Parallel Interface Controller — CD1284
time determining the status of every character. When the receive vector signifies good data, the
CPU removes the data from the FIFO. Checking status is not necessary. Exception data (framing
error, overrun, break, etc.) causes an interrupt with a vector that the CPU can immediately identify
and manage.
The RISC processor is assisted in the process of sending and receiving serial data by specialized
hardware called ‘bit engines’. These logic blocks perform the actual task of sending and receiving
the individual bits of a character, thus removing the task of timing the bit duration from the on-chip
processor. The processor assembles the bits into characters and tests various parameters (for
example, parity, framing, etc.) then places the characters in the FIFO. Since it is managing every
character, special character processing is possible such as looking for and responding to flow-
control characters (XON/XOFF) and performing UNIX^-style character substitutions and range
checking. This reduces interrupt overhead by automatically performing many of the operations that
the CPU normally does. Flow-control, for example, can be performed without CPU involvement.
Those operations can be completely removed from its responsibility.
The CD1284 can be daisy-chained with other CD1284 or CD1400 devices to implement larger and
more complex systems. The Fair Share feature assures equal access for service requests across
multiple devices (Fair Share is not implemented on a parallel port interrupt request).
The parallel channel within the CD1284 implements all protocols defined for the peripheral side by
the IEEE STD 1284. This specification defines four bidirectional protocols that allow a peripheral
device to communicate with a host system (IBM^ PC or equivalent) through the parallel printer
channel. The modes include Reverse Nibble, Reverse Byte (IBM^ PS/2^ style), ECP, and EPP (as
implemented on the Intel^ 80386SL processor). ECP and EPP both operate at data rates as high as
2 Mbytes/sec.
The IEEE 1284 port is implemented as two functional blocks: a data pipeline, which includes the
64-byte FIFO and the DMA interface, and a high-speed state-machine, which controls the parallel
port and implements the slave-side IEEE 1284 protocols. The internal RISC processor assists the
parallel channel by providing interrupt generation, acknowledgment functions, and a data interface
to the Parallel Port registers.
As defined in the IEEE 1284 specification, the CD1284 in ECP mode, provides RLE (run length
encoded) data compression in both directions. This data compression is performed automatically
(if enabled) and is capable of compressing long strings (up to 128 bytes) of identical data into a
two-byte sequence (command/count and data). Since it is common for bit patterns to have large
amounts of identical data, the CD1284 greatly reduces data transmission times in printer
applications.
EPP mode defines a means of sending address and data over the parallel channel much like a
processor address and data interface. This has found widespread use in LAN and SCSI interface
adapters that provide these services on laptop computers.
The following figure shows a possible configuration for a CD1284 in a laser-printer application. In
this example, the CD1284 provides a parallel and serial data interface to a host system or server. It
also provides a serial channel for control communication with the printer console, as well as
general-purpose I/O for static control/status.
Datasheet
13