CD1284 Datasheet, PDF (108/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.0
Detailed Register Descriptions
This section presents a complete and detailed description of each register. Registers have two
formats: 1) full eight bits, where the entire content defines a single function; 2) the register is a
collection of bits, grouped singly or in multiples, defining a function. In the second format, the
descriptions divide the register into its component parts and describe the bits individually. The
order of register presentation corresponds to the register summary tables in Chapter 4.0.
7.1
7.1.1
Global Registers
Channel Access Register
Register Name: CAR
Register Description: Channel Access
Access: Read/Write
Bit 7
Bit 6
Bit 5
Poll
Poll
Poll
Bit 4
Poll
Bit 3
Poll
Bit 2
0
8-Bit Hex Address: 68
Default Value: XX
Bit 1
C1
Bit 0
C0
The CAR provides access to individual channels within the CD1284. The least-significant two bits
of the register select one of the four channels. Before any operation that affects a channel, this
register must be loaded so that channel registers are available to the host. Bit 2 must always be ‘0’.
Bits 7:3 are not used except during Poll-mode operation (see Section 6.3 for details).
C1
C0
Channel Selected
0
0
Channel 0
0
1
Not used
1
0
Channel 2
1
1
Channel 3
7.1.2
Global Firmware Revision Code Register
Register Name: GFRCR
Register Description: Global Firmware Revision Code
Access: Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Firmware Revision Code
Bit 2
8-Bit Hex Address: 4F
Default Value: 25
Bit 1
Bit 0
The GFRCR serves two purposes in the CD1284. First, it displays the revision number of the
firmware in the chip. When a revision to the CD1284 is required, the revision number of the
firmware is incremented by one. The revision code is 24 (hex) for the Revision D device, and 25
(hex) for the Revision E device.
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Datasheet