CD1284 Datasheet, PDF (130/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Bit
Description
7:4
DSRzd, CTSzd, RIzd and CDzd: Each of these bits controls its corresponding input pin. If the bit is set, the
function is enabled and transitions from one-to-zero (zeros detect) generate an SVCREQM* service request.
DTRth3 through DTRth0: These bits form a binary value to determine when the DTR output is negated
(based on the number of characters in the receive FIFO). When the FIFO holds more characters than this
value, DTR is negated, informing the remote to stop transmission. This value must be set to a value
numerically larger than the value set for the receive FIFO threshold in COR3.
DTRth3 DTRth2 DTRth1 DTRth0
Number of Characters in FIFO
0
0
0
0
Automatic DTR mode disabled.
0
0
0
1
1 character
0
0
1
0
2 characters
3:0
•
•
•
•
1
0
1
1
11 characters
1
1
0
0
12 characters
1
1
0
1
1
1
1
0
Not used.
1
1
1
1
7.5.2
Modem Change Option Register 2
Register Name: MCOR2
Register Description: Modem Change Option Register 2
Access: Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
DSRod
CTSod
RIod
CDod
Bit 3
0
Bit 2
0
8-Bit Hex Address: 16
Default Value: 00
Bit 1
0
Bit 0
0
Bit
7:4
3:0
7.5.3
Description
DSRod, CTSod, RIod, CDod: Each of these bits controls its corresponding input pin. If the bit is set, the
function is enabled and transitions from ‘0’-to-‘1’ (ones detect) generate an SVCREQM* service request.
These bits are not used and must be ‘0’.
Modem Signal Value Register 1
Register Name: MSVR1
Register Description: Modem Signal Value Register 1
Access: Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
DSR
CTS
RI
CD
Bit 3
0
Bit 2
0
8-Bit Hex Address: 6C
Default Value: XX
Bit 1
0
Bit 0
RTS
130
Datasheet