CD1284 Datasheet, PDF (43/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

IEEE 1284-Compatible Parallel Interface Controller — CD1284
The CD1284 has a fairness override, the Unfair bit (PACR[0]). If this bit is set, the Fair Share
function of the device is defeated and the MPU posts requests for service regardless of the state of
the external service-request signal. Even when a device in the chain is asserting a request of a
particular type, if another device needs to post a request, it proceeds to do so regardless of the
current state of the request pin because its fair bits are forced true. If it is upstream from the device
already posting the request and if the CPU pipeline has not yet responded to the previous request
from the downstream device, then the upstream device accepts the acknowledge on arrival and
overrides the priority normally given to the device that made the first request. This is useful in
system designs that wire-OR the request signals together, rather than using an external gate, since
in these cases, without overriding fairness a request of one type within a device holds off a request
of a different type. For example, an existing transmit request prevents the device from posting a
receive request.
Note:
(IMPORTANT) If no CD1284 in the chain has a pending request, the daisy-grant passes by the last
and none respond. This causes the bus cycle to hang (no DTACK* is generated). The only time this
happens is when an error condition outside the CD1284s cause the CPU to respond to a request that
is not made. A mechanism can be provided to terminate or abort the bus cycle if this error occurs.
This is accomplished with timeout circuitry. Otherwise the DPASS* output of the last CD1284
activates an abort condition. Other devices, such as the CD1400, can share the daisy-chain
mechanism and can be connected to the DPASS* output of the last CD1284 in the chain. The actual
implementation is system-dependent, but it is important to provide some way for the CPU to know
that the cycle did not complete normally if no device responds to the acknowledge cycle.
5.4
Parallel Port Service Requests
The parallel port service-request structure of the CD1284 is slightly different from that of the serial
ports. These differences are highlighted in this section.
Service requests can derive from two internal sources: the data pipeline or the parallel port state
machine (see Figure 7 on page 45). If the data pipeline internal service request becomes active, the
Pipeline bit (PIR[5]) is set; likewise, if the parallel port state machine internal service request
becomes active, the PPort bit (PIR[6]) is set. Internal service requests from these sources are
monitored through the Pipeline and PPort bits by microcode running in the internal MPU. When
either (or both) of these bits are detected active, the microcode sets the PPireq bit (PIR[7]). The
PPireq bit is also mirrored by the SRP bit (SVRR[3]). The SVRR is useful in polled systems
because it allows the detection of DMA service requests, as well as parallel port service requests
with a single register read operation.
Both internal sources of service requests within the parallel channel have their own enable
functions. Interrupts from the data pipeline are enabled through the PFCR; interrupts from the
parallel port state machine are enabled through the PCIER.
The PFCR has two enable bits: one for normal interrupts (such as tagged data being received), and
one for data errors (such as a CPU write to a holding register that already holds data). The first type
of interrupt is enabled through the IntEn bit (PFCR[4]). The second type of interrupt is enabled
through the ErrEn bit (PFCR[1]). Note that IntEn must be set for ErrEn to generate an interrupt;
however, the CPU need not enable error interrupts if it does not require notification of these types
of errors. The error interrupt is generated if the DataErr bit (PFSR[0]) is a non-zero. In this case,
the DER indicates the cause of the error interrupt.
The parallel channel-control state machine can generate six types of interrupts. Each of these has
its own enable bit in the PCIER:
Datasheet
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