CD1284 Datasheet, PDF (75/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

IEEE 1284-Compatible Parallel Interface Controller — CD1284
5.11.4
5.11.5
Byte-alignment issues on transfers to/from the FIFO are avoided by having the FIFO byte-oriented
with 2-byte word packing/unpacking occurring between the DMABUF register and PFHR1 and
PFHR2. The order of byte transfers to/from the DMA buffer is controlled by the BYTESWAP
input. If BYTESWAP is high, the upper byte (bits 15:8) is transferred first. If BYTESWAP is low,
the lower byte (bits 7:0) is transferred first.
Data transfers to/from the CPU are initiated by a DMA request whenever the quantity of data or
space in the FIFO equals or exceeds the threshold value stored in the PFTR. The DMA request is
deasserted during the DMA cycle determined by the logic to be the last because of filling/emptying
the FIFO or the presence of tagged data in the receive pipeline.
Receive Direction
In the receive direction (DMAdir = 0), the first two bytes of data placed into the FIFO by the
parallel port are immediately moved into the data pipeline, PFHR1 and PFHR2 (Figure 11 on
page 78). This is done in part to make the tagged status of the data visible to the pipeline control
logic. If RLEen is ‘0’, any tagged data from the FIFO must move through the pipeline. However,
tagged data cannot be transferred to the CPU by a DMA transfer from the DMABUF register.
Therefore, the presence of tagged data in the pipeline causes an interrupt to the CPU. The CPU
must then examine the HRSR to determine the pipeline status.
If there is tagged data in one of the holding registers, the CPU must read that register to empty it
and clear the tag. If more data is available in the FIFO, data immediately moves forward to fill the
pipeline. If the FIFO is empty, the pipeline does not move. If the CPU emptied PFHR2 and PFHR1
is full, the data in PFHR1 moves forward to PFHR2 only if the FIFO is not empty.
The pipeline logic keeps the pipeline full in the receive direction. The value in the threshold
register is tested against the quantity of data in the FIFO. Therefore, a number of characters equal
to the PFTR-threshold value plus two must arrive before a DMA request is made to the CPU to
remove the data.
Receiving Compressed Data
RLE compressed-data sequences that consist of a tagged RLE count followed by the compressed
data character are stored in the FIFO in compressed form. As data moves from the FIFO into the
data pipeline, the tag bit is inspected. If the tagged data is an RLE count (HostAck signal is high)
and RLEen is true, the RLE count is loaded into the RLCR instead of PFHR1; the next data
character is loaded into PFHR1. Decompression occurs by holding the compressed character in
PFHR1 as copies of the character are shifted forward into PFHR2. As each copy of the character is
shifted, the RLCR value decrements. When the RLCR reaches zero, the hold on PFHR1 is released
and it can shift forward in the pipeline as ordinary data.
Tagged data from the FIFO is recognized as an ECP mode address and shifts into the pipeline
where it causes an interrupt to the CPU to remove the tagged data from the pipeline. If RLEen is
‘0’, all tagged data from the FIFO is shifted into the pipeline and produces CPU interrupts.
If an immediate termination occurs between the reception of the RLE count and the corresponding
data, then the RLE count is stored in RLCR and the next data byte received in ECP mode is
uncompressed into the FIFO (based on the values in RLCR and if RLEen is still set). If the next
byte received in ECP mode is a new RLE count, then that value overwrites the old value in RLCR.
Datasheet
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