CD1284 Datasheet, PDF (46/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Figure 7. Interrupt Generation Logic (Continued)
A1284 signal
transition from low-
to-high, and
A1284(ODR[3]) = 1
nInit signal
HstBsy signal
HstClk signal
transition from ^{transition from low- transition from low-}
low-to-high, and ^{to-high, and}
to-high, and
nInit(ODR[2]) = 1 ^{HstBsy(ODR[1]) = 1 HstClk(ODR[0]) = 1}
Interface must be in COMPATIBLE MODE
when MANMD (PCR.7) is set or MANMD wil
have no affect
MANMD
(PCR[7])
A1284 signal
nInit signal
transition from
transition from
high-to-low, and high to low, and
A1284(ZDR[3]) = 1 nInit(ZDR[2]) = 1
HstBsy signal
HstClk signal
transition from high- transition from
to-low, and
high-to-low, and
HstBsy(ZDR[1]) = 1 HstClk(ZDR[0]) = 1
SIGCH
(PCIER[4])
Host has reversed the direction of the interface from ECP-
forward to ECP-reverse by driving nReverseRequest (nInit)
signal low.
EPP address received
on parallel port
EPPAW
(PCIER[3])
Host has changed the direction of the interface from ECP-
reverse to ECP-forward by driving nReverseRequest
(nInit) signal high.
In Compatible mode, the
host has requested the
peripheral to re-initialize
itself (nInit went low).
(PCISR[5]) (PCISR[4]) (PCISR[3]) (PCISR[2]) (PCISR[1]) (PCISR[0])
NEGCH SIGCH EPPAW DIRCH IDREQ NINIT
nInit
(PCIER[0])
INTEN
(PFCR[4])
SIGCH
(PCISR[4])
EPPAW
(PCISR[3])
DIRCH
(PCISR[2])
NINIT
(PCISR[0])
PPORT
(PIR[6])
46
Datasheet