CD1284 Datasheet, PDF (136/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.6.10
Transmit Clock Option Register
Register Name: TCOR
Register Description: Transmit Clock Option
Access: Read/Write
Bit 7
Bit 6
Bit 5
X
X
X
Bit 4
X
Bit 3
X
Bit 2
ClkSel2
8-Bit Hex Address: 76
Default Value: 01
Bit 1
ClkSel1
Bit 0
ClkSel0
The TCOR selects the clock source which drives the TBPR. The value in ClkSel[2:0] selects one of
five possible clocks generated from the master clock (CLK).
ClkSel2
0
0
0
0
1
1
1
1
ClkSel1
0
0
1
1
0
0
1
1
ClkSel0
0
1
0
1
0
1
0
1
Clock Selected
Clk0 (CLK ÷ 8)
Clk1 (CLK ÷ 32)
Clk2 (CLK ÷ 128)
Clk3 (CLK ÷ 512)
Clk4 (CLK ÷ 2048)
Not used.
7.7
7.7.1
Channel Registers — Parallel Pipeline
Data Error Register
Register Name: DER
Register Description: Data Error
Access: Read only
Bit 7
Bit 6
Bit 5
DMAwrerr
DMArderr
Bufwrerr
Bit 4
Bufrderr
Bit 3
HR1wrerr
Bit 2
HR1rderr
8-Bit Hex Address: 33
Default Value: 00
Bit 1
HR2wrerr
Bit 0
HR2rderr
The bits in this read-only register indicate read/write errors involving the DMABUF register and
the Data Pipeline registers. The DataErr bit (PFSR[0]) is the logical OR of these eight Error Status
bits.
Reading this register has no effect on the error status. A write to this register clears all the bits,
which cannot be written by the user. Host software should clear this register (write x’00) after
completing an error service-acknowledge procedure. This bit is provided primarily as an aid to
driver software development. Data errors should never occur under normal circumstances.
This register is cleared during device reset.
136
Datasheet