SE7210TP1-E Datasheet, PDF (42/145 Pages) Intel Corporation – Intel® Server Board Technical Product Specification

Intel® Server Board SE7210TP1-E TPS
Functional Architecture
3.4.5.1.1
Adaptec 7901 Summary of Features
The Adaptec 7901 contains the following SCSI performance features:
z SCSI data transfers up to 320 MB/sec
z 8- or 16-bit SCSI data path
z SCSI offsets to 254 transfers
z Advanced multimode I/O cell is compatible with LVD or SE devices
z Extensive hardware support for disconnect/reconnect and scatter/gather
z Full support for both initiator and target operations
z Full support for domain validation, which provides two levels (basic and enhanced) of
SCSI bus configuration testing to help ensure Ultra320 and Ultra160 SCSI topologies
operate at optimum speed
z Multiple target ID enables responses to multiple IDs as a SCSI target
z Full support for CRC for 16-bit SCSI synchronous data transfers. CRC detects data
integrity errors that would not be detected by simple parity checking used by previous
SCSI generations. The higher data rates achieved on existing LVD cable configurations
mandated this improved data integrity feature.
z Supports Quick Arbitration and Selection (QAS) and SCSI arbitration fairness. QAS
reduces overhead when bus control is transferred between devices. Arbitration fairness
prevents devices from hogging the bus by guaranteeing each device a chance to
arbitrate.
z Supports Seamless Streaming technology, which allows full implementation of SCSI
packet protocol for sending many commands, receiving many statuses, and
transferring data for many commands during one SCSI connection. There is virtually no
delay between packets for different commands.
The Adaptec 7901 has a 133 MHz, 64-bit PCI/PCI-X Host Interface that supports the following
PCI features:
z PC2001 compliant
z Direct pin connection to the PCI/PCI-X interface, from 133-MHz, 64-bit interface down
to PCI 33-MHz, 32-bit interface
z Leading and trailing offset bytes on a 32- or 64-bit bus
z Performance-enhanced 32-bit operating mode allows 32-bit data transactions with 32-
and 64-bit addressing (SAC/DAC)
z 3.3-V/5-V PCI and 3.3-V PCI-X interfaces provide flexibility for designing high
performance, low-power systems
z PCI bus master and slave timing referenced to PCLK
z PCI bus-programmable Latency Timer, Cache Size, and Interrupt Line Select registers
z Supports external read access to the BIOS FLASH on the host bus adapter (HBA)
z Supports SEEPROM read and write word access with an Adaptec utility
z Medium PCI target device select response time
z Streaming PCI-enhanced master Direct Memory Access (DMA) read and write burst
commands
z PCI bus address and data parity generation and checking
z Supports PCI PERR# and SERR# requirements
z Supports up to five outstanding split completions
z PCI bus address and data phase error generation for checking host and device error
support
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