SE7210TP1-E Datasheet, PDF (23/145 Pages) Intel Corporation – Intel® Server Board Technical Product Specification

Intel® Server Board SE7210TP1-E TPS
Functional Architecture
3.1.3
Microcode
IA32 processors have the capability of correcting specific errata through the loading of an Intel-
supplied data block (microcode update). The BIOS is responsible for storing the update in
nonvolatile memory and loading it into each processor during POST. The BIOS performs all the
recommended update signature verification prior to storing the update in the Flash.
3.1.4
Processor Cache
The BIOS enables all levels of processor cache as early as possible during POST. There are no
user options to modify the cache configuration, size or policies. All detected cache sizes are
reported in the SMBIOS Type 7 structures. The largest and highest level cache detected is
reported in BIOS Setup
3.1.5
Hyper-Threading Technology
Intel^® Pentium^® 4 processors support Hyper-Threading Technology. The BIOS will detect
processors that support this feature and will enable the feature during POST. BIOS Setup
provides an option to selectively enable or disable this feature. The default behavior is enabled.
The BIOS will create additional entries in the ACPI MP tables to describe the virtual processors.
The SMBIOS Type 4 structure will show only the physical processors installed.
3.2 Intel E7210 Chipset
The Intel E7210 chipset consists of the following devices:
• Intel 827210 Memory Controller Hub (MCH) with Accelerated Hub Architecture (AHA)
bus
• Intel 6300ESB I/O Controller Hub with AHA bus
• Intel 82802AC (8 Mbit) Firmware Hub (FWH)
3.2.1
Intel 827210 Memory Controller Hub (MCH)
The MCH is a centralized controller for the system bus, the memory bus and the Accelerated
Hub Architecture interface. The 6300ESB I/O is a centralized controller for the Server Board
SE7210TP1-E’s I/O paths. The FWH provides the nonvolatile storage of the BIOS. The
component combination provides the chipset interfaces as shown in Figure 3.
Revision 2.0
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