SE7210TP1-E Datasheet, PDF (38/145 Pages) Intel Corporation – Intel® Server Board Technical Product Specification

Intel® Server Board SE7210TP1-E TPS
Functional Architecture
3.4.2
DMA Channels
DMA Channel
Number
0
1
2
3
4
5
6
7
Table 6. DMA Channels
Data Width
System Resource
8 or 16 bits
8 or 16 bits
8 or 16 bits
8 or 16 bits
8 or 16 bits
16 bits
16 bits
16 bits
Open
Diskette drive
DMA controller
Open
Open
Open
3.4.3
Interrupts
The interrupts can be routed through the Advanced Programmable Interrupt Controller (APIC)
portion of the 6300ESB I/O component. The APIC is supported in Windows* 2000 Server and
Windows XP and supports a total of 24 interrupts.
IRQ
NMI
I/O channel check
Table 7. Interrupts
System Resource
0
Reserved, interval timer
1
Reserved, keyboard buffer full
2
Reserved, cascade interrupt from slave PIC
3
COM2 ^{(Note 1)}
4
COM1 ^{(Note 1)}
6
Diskette drive
8
Real-time clock
9
Reserved for 6300ESB I/O system management bus
10
User available
11
User available
12
Onboard mouse port (if present, else user available)
13
Reserved, math coprocessor
14
Primary IDE (if present, else user available)
15
Secondary IDE (if present, else user available)
16
USB UHCI controller 1 (through PIRQA)
17
User available (through PIRQB)
18
6300ESB I/O USB controller 3 (through PIRQC)
19
6300ESB I/O USB controller 2 (through PIRQD)
20
6300ESB I/O LAN (through PIRQE)
21
User available (through PIRQF)
22
User available (through PIRQG)
23
6300ESB I/O USB 2.0 EHCI controller/User available (through PIRQH)
Notes:
1. Default, but can be changed to another IRQ.
24
Revision 2.0