SE7210TP1-E Datasheet, PDF (27/145 Pages) Intel Corporation – Intel® Server Board Technical Product Specification

Intel® Server Board SE7210TP1-E TPS
Functional Architecture
3.2.10
Low Pin Count (LPC) Interface
The 6300ESB I/O implements an LPC Interface as described in the Low Pin Count Interface
Specification, Revision 1.1. The Low Pin Count (LPC) Bridge function of the 6300ESB I/O
resides in PCI Device 31: Function 0. In addition to the LPC bridge interface function, D31:F0
contains other functional units including DMA, interrupt controllers, timers, power management,
system management, GPIO, and RTC.
3.2.11
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the
seven DMA channels can be programmed to support fast Type-F transfers.
The 6300ESB I/O supports two types of DMA (LPC and PC/PCI). LPC DMA and PC/PCI DMA
use the 6300ESB I/O’s DMA controller. The PC/PCI protocol allows PCI-based peripherals to
initiate DMA cycles by encoding requests and grants via two PC/PC REQ#/GNT# pairs. LPC
DMA is handled through the use of the LDRQ# lines from peripherals and special encoding on
LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the
LPC interface. Channels 0–3 are 8 bit channels. Channels 5–7 are 16 bit channels. Channel 4
is reserved as a generic bus master request.
The timer/counter block contains three counters that are equivalent in function to those found in
one 82C54 programmable interval timer. These three counters are combined to provide the
system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock
source for these three counters.
The 6300ESB I/O provides an ISA-compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two 82C59 interrupt controllers. The two interrupt controllers are
cascaded so that 14 external and two internal interrupts are possible. In addition, the 6300ESB
I/O supports a serial interrupt scheme. All of the registers in these modules can be read and
restored. This is required to save and restore system state after power has been removed and
restored to the platform.
3.2.12
Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA-compatible PIC described in the previous section, the 6300ESB
I/O incorporates the Advanced Programmable Interrupt Controller (APIC).
3.2.13
Universal Serial Bus (USB) Controller
The 6300ESB I/O contains an Enhanced Host Controller Interface Specification for Universal
Serial Bus, Revision 1.0 -compliant host controller that supports USB high-speed signaling.
High-speed USB 2.0 allows data transfers up to 480 Mb/s which is 40 times faster than full-
speed USB. The 6300ESB I/O also contains four Universal Host Controller Interface (UHCI)
controllers that support USB full-speed and low-speed signaling.
Revision 2.0
13