SE7210TP1-E Datasheet, PDF (31/145 Pages) Intel Corporation – Intel® Server Board Technical Product Specification

Intel® Server Board SE7210TP1-E TPS
Functional Architecture
✏ ^NOTES
To be fully compliant with all applicable DDR SDRAM memory specifications, the board
should be populated with DIMMs that support the Serial Presence Detect (SPD) data
structure. This allows the BIOS to read the SPD data and program the chipset to accurately
configure memory settings for optimum performance. If non-SPD memory is installed, the
BIOS will attempt to correctly configure the memory settings, but performance and reliability
may be impacted or the DIMMs may not function under the determined frequency.
For ECC functionality, all installed DIMMs must be ECC. If both ECC and non-ECC DIMMs
are used, ECC will be disabled and will not function.
3.3.1
Memory Configurations
The Intel 827210 MCH component provides two features for enhancing memory throughput:
• Dual Channel memory interface. The board has two memory channels, each with two
DIMM sockets.
• Dynamic Addressing Mode. Dynamic mode minimizes overhead by reducing memory
accesses.
Table 4 summarizes the characteristics of dual and single channel configurations with and
without the use of Dynamic Mode.
Table 4. Characteristics of Dual/Single Channel Configuration with/without Dynamic Mode
Throughput
Level
Highest
Lowest
Configuration
Dual Channel with Dynamic Mode
Dual Channel without Dynamic Mode
Single Channel with Dynamic Mode
Single Channel without Dynamic Mode
Characteristics
All DIMMs matched
(Example configurations are shown in Figure 5)
DIMMs matched from Channel A to Channel B
DIMMs not matched within channels
(Example configuration is shown in Figure 6)
Single DIMM or DIMMs matched with a channel
(Example configurations are shown in Figure 7)
DIMMs not matched
(Example configurations are shown in Figure 8)
Revision 2.0
17