SE7210TP1-E Datasheet, PDF (29/145 Pages) Intel Corporation – Intel® Server Board Technical Product Specification

Intel® Server Board SE7210TP1-E TPS
Functional Architecture
3.2.15
GPIO
Various general purpose inputs and outputs are provided for custom system design. The
number of inputs and outputs varies depending on the 6300ESB I/O configuration. All unused
GPI pins must be pulled high or low, so that they are at a predefined level and do not cause
undue side effects.
3.2.16
Enhanced Power Management
The 6300ESB I/O’s power management functions include enhanced clock control, local and
global monitoring support for 14 individual devices, and various low-power (suspend) states
(e.g., Suspend-to-DRAM and Suspend-to-Disk). A hardware-based thermal management circuit
permits software-independent entrance to low-power states. The 6300ESB I/O contains full
support for the Advanced Configuration and Power Interface (ACPI) Specification, Revision
2.0b.
3.2.17
System Management Bus (SMBus 2.0)
The 6300ESB I/O contains an SMBus Host interface that allows the processor to communicate
with SMBus slaves. This interface is compatible with most I2C devices. Special I2C commands
are implemented. The 6300ESB I/O’s SMBus host controller provides a mechanism for the
processor to initiate communications with SMBus peripherals (slaves). Also, the 6300ESB I/O
supports slave functionality, including the Host Notify protocol. Hence, the host controller
supports eight command protocols of the SMBus interface (see System Management Bus
(SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write
Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
3.3 Memory Subsystem
The Intel 827210 Memory Controller Hub (MCH) is one component of the Intel E7210 chipset.
The MCH is a centralized controller for the system bus, the memory bus and the accelerated
hub architecture interface.
The server board SE7210TP1-E provides four DIMM slots and supports a maximum memory
capacity of 4 GB. The DIMM organization is x72, which includes eight ECC check bits. ECC from
the DIMMs are passed through to the processor’s system bus. Memory scrubbing, single-bit
error correction and multiple-bit error detection is supported. Memory can be implemented with
either single-sided (one row) or double-sided (two row) DIMMs.
Revision 2.0
15