SE7210TP1-E Datasheet, PDF (116/145 Pages) Intel Corporation – Intel® Server Board Technical Product Specification

Intel® Server Board SE7210TP1-E TPS
Error Reporting and Handling
6. Error Reporting and Handling
This section documents the types of system bus error conditions monitored by the Intel Server Board
SE7210TP1-E.
6.1 Error Sources and Types
One of the major requirements of server management is to correctly and consistently handle
system errors. System errors, which can be disabled and enabled individually or as a group, can
be categorized as follows:
• PCI bus
• Memory single- and multi-bit errors
• Sensors
• Processor internal errors, bus/address errors, thermal trip errors, temperatures and
voltages, and GTL voltage levels
• Errors detected during POST, logged as ‘POST errors’
On the SE7210TP1-E platform, the Winbond* chip manages general hardware monitoring
sensors on a hardware level; however action is only taken by software (i.e., an application such
as LANDesk™ Client Manager).
6.1.1
PCI Bus Errors
The PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and
system errors, respectively. In the case of PERR#, the PCI bus master has the option to retry
the offending transaction, or to report it using SERR#. All other PCI-related errors are reported
by SERR#. SERR# is routed to NMI if enabled by BIOS.
6.1.2
Processor Bus Errors
The MCH supports the data integrity features supported by the Pentium® Pro bus, including
address, request, and response parity. The E7210 chipset always generates ECC data while it
is driving the processor data bus, although the data bus ECC can be disabled or enabled by
BIOS. It is enabled by default.
6.1.3
Memory Bus Errors
The MCH is programmed to flag and log multi-bit errors (MBEs). The MCH then triggers an SMI
to the 6300ESB I/O and the 6300ESB I/O asserts the SMI# signal. BIOS then logs the errors in
the event log.
6.2 BIOS Error Messages, POST Codes, and BIOS Beep Codes
The BIOS indicates the current testing phase during POST by writing a hex code to I/O location
80h. If errors are encountered, error messages or codes will either be displayed to the video
screen, or if an error has occurred prior to video initialization, errors will be reported through a
series of audio beep codes. POST errors are logged in to the SEL.
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