SE7210TP1-E Datasheet, PDF (36/145 Pages) Intel Corporation – Intel® Server Board Technical Product Specification

Intel® Server Board SE7210TP1-E TPS
Functional Architecture
3.4 I/O Sub-System
The I/O sub-system is made up of several components: the 6300ESB I/O providing the PCI-X
interfaces for the three PCI slots and riser slot on board 3, the on-board SCSI controller, the on-
board Ethernet controllers, the onboard video controller, Super IO chip, and Management Sub-
system. This section describes the function of each I/O interface and how they operate on the
SE7210TP1-E server board.
3.4.1
PCI Sub-System
The primary I/O bus for the Intel Server Board SE7210TP1-E is PCI, with two independent PCI
buses. The PCI buses comply with the PCI Local Bus Specification, Rev 2.2. The PCI bus is
directed through the Intel 6300ESB I/O Controller Hub. The table below lists the characteristics
of the two PCI bus segments.
PCI Bus Segment
P32-A
P64-A
P64-A
Table 5: PCI Bus Segment Characteristics
Voltage Width
Speed
5V
32-bits 33 MHz
3.3 V
3.3 V
64-bits 66 MHz
64-bits 66 MHz
Type
PCI
PCI-X
PCI-X
PCI I/O Card Slots
1 - capable of supporting full-
length PCI add-in cards.
Internal component use.
3 - capable of supporting full-
length PCI-X add-in cards
1 - riser slot supporting low-
profile add-in cards (Only on
board 3)
3.4.1.1
P32-A: 32-bit, 33MHz PCI Sub-system
All 32-bit, 33-MHz PCI I/O for the SE7210TP1-E server board is directed through the 6300ESB
I/O. The 32-bit, 33-MHz PCI segment created by the 6300ESB I/O is known as the P32-A
segment. The P32-A segment supports the following devices:
• One 32-bit PCI slot
• 2D/3D Graphics Accelerator: ATI Rage XL Video Controller
• SIO Chip: Winbond* W83627 HF-AW Super I/O
• Hardware monitoring sub-system: SMBUS.
3.4.1.2
P64-A: 64-bit, 66MHz PCI Subsystem
There is one 64-bit PCI-X bus segment directed through the 6300ESB I/O. P64-A supports the
interface for the on-board Adaptec* 7901 Ultra 320 SCSI controller in addition to supporting up
a maximum of three PCI slots.
3.4.1.3
Scan Order
The BIOS assigns PCI bus numbers in a depth-first hierarchy, in accordance with the PCI Local
Bus Specification. When a bridge device is located, the bus number is incremented in exception
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Revision 2.0