SE7210TP1-E Datasheet, PDF (39/145 Pages) Intel Corporation – Intel® Server Board Technical Product Specification

Intel® Server Board SE7210TP1-E TPS
Functional Architecture
3.4.4
PCI Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected between
the PCI bus connectors and onboard PCI devices. The PCI specification specifies how
interrupts can be shared between devices attached to the PCI bus. In most cases, the small
amount of latency added by interrupt sharing does not affect the operation or throughput of the
devices. In some special cases where maximum performance is needed from a device, a PCI
device should not share an interrupt with other PCI devices. Use the following information to
avoid sharing an interrupt with a PCI add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
• INTA: By default, all add-in cards that require only one interrupt are in this category. For
almost all cards that require more than one interrupt, the first interrupt on the card is also
classified as INTA.
• INTB: Generally, the second interrupt on add-in cards that require two or more interrupts
is classified as INTB. (This is not an absolute requirement.)
• INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a
fourth interrupt is classified as INTD.
The 6300ESB I/O has eight programmable interrupt request (PIRQ) input signals. All PCI
interrupt sources either onboard or from a PCI add-in card connect to one of these
PIRQ signals. Some PCI interrupt sources are electrically tied together on the Server Board
SE7210TP1-E and therefore share the same interrupt. Table 8 shows an example of how the
PIRQ signals are routed.
For example, using Table 8 as a reference, assume an add-in card using INTB is plugged into
PCI bus connector 3. In PCI bus connector 3, INTB is connected to PIRQA, which is already
connected to the Promise PDC20319 Controller. The add-in card in PCI bus connector 3 now
shares an interrupt with the onboard interrupt source.
IDSEL
P_INTA*
P_INTB*
P_INTC*
P_INTD*
P_INTE*
P_INTF*
PX_INTA*
PX_INTB*
PX_INTC*
PX_INTD*
PX_IRQ*
REQ/GNT
P_AD18
INTA
INTB
INTC
SCSI_A*
1
PCI 64 bit
SLOT1
Table 8. PCI Interrupt Routing Map
PX_AD19 PX_AD20 PX_AD17 P_AD16
INTB
INTC
INTD
INTA
2
PCI 64 bit
SLOT2
INTC
INTD
INTA
INTB
3
PCI 64 bit
SLOT3
IRQ3
0
SCSI
INTF
0
ATI
RAGE
P_AD17
INTB
1
LAN
10/100
P_AD18
INTA
INTB
INTC
INTD
PIN B2, INTE
PIN B4, INTE
2
PCI 32 bit
SLOT6
Revision 2.0
25