SE7210TP1-E Datasheet, PDF (119/145 Pages) Intel Corporation – Intel® Server Board Technical Product Specification

Intel® Server Board SE7210TP1-E TPS
Error Reporting and Handling
6.2.2
Port 80h POST Codes
During the POST, the BIOS generates diagnostic progress codes (POST codes) to I/O port 80h.
If the POST fails, execution stops and the last POST code generated is left at port 80h. This
code is useful for determining the point where an error occurred.
Check
point
03
04
05
06
08
C0
C1
C2
C5
C6
C7
0A
0B
0C
Table 59: POST Code Checkpoints
Diagnostic LED Decoder
G=Green, R=Red, A=Amber
Hi
Low
OF OF G
G
F
F
OF G
F
OF OF
F
F
OF G
F
OF G
F
OF G
F
G
OF
F
G
OF OF OF
F
F
F
R
R
OF OF
F
F
R
R
OF G
F
R
R
G
OF
F
R
A
OF G
F
R
A
G
OF
F
R
A
G
G
G
OF G
OF
F
F
G
OF G
G
F
G
G
OF OF
F
F
Diagnostic LED Decoder
G=Green, R=Red, A=Amber
Disable NMI, Parity, video for EGA, and DMA
controllers. Initialize BIOS, POST, Runtime data area.
Also initialize BIOS modules on POST entry and GPNV
area. Initialized CMOS as mentioned in the Kernel
Variable "wCMOSFlags."
Check CMOS diagnostic byte to determine if battery
power is OK and CMOS checksum is OK. Verify CMOS
checksum manually by reading storage area. If the
CMOS checksum is bad, update CMOS with power-on
default values and clear passwords. Initialize status
register A.
Initializes data variables that are based on CMOS setup
questions. Initializes both the 8259 compatible PICs in
the system
Initializes the interrupt controlling hardware (generally
PIC) and interrupt vector table.
Do R/W test to CH-2 count reg. Initialize CH-0 as
system timer. Install the POSTINT1Ch handler. Enable
IRQ-0 in PIC for system timer interrupt.
Traps INT1Ch vector to "POSTINT1ChHandlerBlock."
Initializes the CPU. The BAT test is being done on KBC.
Program the keyboard controller command byte is being
done after Auto detection of KB/MS using AMI KB-5.
Early CPU Init Start -- Disable Cache - Init Local APIC
Set up boot strap processor Information
Set up boot strap processor for POST
Enumerate and set up application processors
Re-enable cache for boot strap processor
Early CPU Init Exit
Initializes the 8042 compatible Key Board Controller.
Detects the presence of PS/2 mouse.
Detects the presence of Keyboard in KBC port.
Revision 2.0
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