SE7210TP1-E Datasheet, PDF (104/145 Pages) Intel Corporation – Intel® Server Board Technical Product Specification

Intel® Server Board SE7210TP1-E TPS
Platform Management Architecture
The National Semiconductor PC87431 integrated management controller uses the Power Good
signal to monitor whether the power supply is on and operational, and to confirm whether the
actual system power state matches the intended system on/off power state that was
commanded with the Power On signal.
De-assertion of the Power Good signal generates an interrupt that the National Semiconductor
PC87431 integrated management controller uses to detect either power subsystem failure or
loss of AC power. If AC power is suddenly lost, the National Semiconductor PC87431 integrated
management controller:
1. Immediately asserts system reset
2. Powers down the system
3. Waits for configured system off time (depending on configuration)
4. Attempts to power the system on (depending on configuration)
5.2.1.1
Power-up Sequence
When turning on the system power in response to one of the event occurrences listed in
Table 52 below, the National Semiconductor PC87431 integrated management controller
executes the following procedure:
1. The National Semiconductor PC87431 integrated management controller asserts Power
On and waits for the power subsystem to assert Power Good. The system is held in
reset.
2. The National Semiconductor PC87431 integrated management controller sends a Set
ACPI Power State command, indicating an S0 state to all management controllers
whose SDR management device records indicate that they should receive the
notification.
3. The National Semiconductor PC87431 integrated management controller initializes all
sensors to their Power On initialization state. The Init Agent is run.
4. The National Semiconductor PC87431 integrated management controller attempts to
boot the system by running the FRB algorithm.
5.2.1.2
Power-down Sequence
To power down the system, the National Semiconductor PC87431 integrated management
controller effectively performs the sequence of power-up steps in reverse order. This operation
can be initiated by one of the event occurrences listed in Table 52 and proceeds as follows:
1. The National Semiconductor PC87431 integrated management controller asserts system
reset (de-asserts Power Good).
2. If enabled, the National Semiconductor PC87431 integrated management controller
sends a Set ACPI Power State command, indicating an S0 state to all management
controllers whose SDR management device records indicate that they should receive
the notification.
3. The National Semiconductor PC87431 integrated management controller de-asserts the
Power On signal.
4. The power subsystem turns off system power upon de-assertion of the Power On signal.
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