SE7210TP1-E Datasheet, PDF (12/145 Pages) Intel Corporation – Intel® Server Board Technical Product Specification

Intel® Server Board SE7210TP1-E TPS
List of Tables
Table 33. Boot Settings Configuration Submenu........................................................................ 60
Table 34. Boot Device Priority Submenu .................................................................................... 61
Table 35. Boot Disk Drives Submenu ........................................................................................ 62
Table 36. Removable Drives Submenu ...................................................................................... 62
Table 37. CD/DVD Drives Submenu........................................................................................... 63
Table 38. Security Menu ............................................................................................................. 63
Table 39. Server Menu ............................................................................................................... 64
Table 40. System Managment Submenu.................................................................................... 66
Table 41. Serial Console Features Submenu ............................................................................. 67
Table 42. Event Log Configuration Submenu ............................................................................. 68
Table 43. Exit Menu .................................................................................................................... 68
Table 44: Supported Wake Events ............................................................................................. 70
Table 45. Effects of Pressing the Power Switch ......................................................................... 71
Table 46. Power States and Targeted System Power ................................................................ 71
Table 47: Supported Channel Assigments ................................................................................. 78
Table 48: LAN Channel Capacity................................................................................................ 80
Table 49: LAN Channel Specifications ....................................................................................... 81
Table 50: PEF Action Priorities ................................................................................................... 86
Table 51. National Semiconductor PC87431 integrated management controller Factory Default
Event Filters ......................................................................................................................... 86
Table 52: Power Control Initiators............................................................................................... 91
Table 53: System Reset Sources and Actions............................................................................ 92
Table 54: Chassis ID LEDs......................................................................................................... 94
Table 55: Fault/Status LED......................................................................................................... 95
Table 56: National Semiconductor PC87431 integrated management controller Built-in Sensors99
Table 57: SE7520JR2 Platform Sensors for Essentials Management...................................... 100
Table 58: POST Error Messages and Handling........................................................................ 103
Table 59: POST Code Checkpoints.......................................................................................... 105
Table60: Bootblock Initialization Code Checkpoints ................................................................. 107
Table61: Bootblock Recovery Code Checkpoints..................................................................... 109
Table62 : POST Error Beep Codes .......................................................................................... 110
Table63 : BIOS Recovery Beep Codes .................................................................................... 110
Table 64. Bus Initialization Checkpoints ................................................................................... 110
Table 65. Upper Nibble High Byte Functions............................................................................ 110
Table 66. Lower Nibble High Byte Functions............................................................................ 111
xii
Revision 2.0