MB86613S Datasheet, PDF (96/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
Table 7- 1 Adr00h bit description
Bit
----
15
Field Name
reset
-------------- ----
PWE_EN
0b
description
--------------------------------------
“1” at this bit reduces the power consumption during idle
(no 1394 connection).
9
OHCImode
0b
Setting “0” at this bit enables OHCI1.0 mode
Setting “1” at this bit enables OHCI1.1 mode.
4
PCI_PME#
0b
Setting ”1” at this bit enables the PCI PME# signal.
3
VENDOR_ID
0b
Setting ”0” at this bit shows Fujitsu Vendor ID. Normally set to ”0”.
2
DEBUG_MODE 1b
Setting ”1” at this bit enables to access the debug register and
EEPROM configuration write through PCI configuration register.
Normally set to ”0”.
1
BYTE_SWAP
1b
Setting ”1” at this bit performs the byte swapping for the data of the 1394
configuration ROM access. Normally set to ”0”.
0
BIOS_EN
1b
Setting ”1” at this bit sets the ExpantionROMBaseAddress,
rom_enable bit. MB86613S does not support Expantion ROM, This bit
is set to “0”.
Please write “0” to the reserved bits of Adr 00h.
To write with following format through PCI configuration register 14h, MB86613S EEPROM configuration
registers are also programmed without external serial EEPROM.
31
24 23
16 15
87
0
EEP_Config_Data
EEP_Adr
WR_EN
Fig. 7.4.1 EEPROM configuration Register
Bit
Field Name
rwu
---- -------------- ---
31:16 EEP_Config_Data w
reset
----
00h
description
-----------------------------------
Set the write data to EEPROM configuration
15:12 EEP_Adr
w
0h
Set the Address of EEPROM configuration
8
WR_EN
w
0b
“1” enables the data write to EEPROM configuration.
Caution : To use this feature, external EEDO pin must be open.
: EEP_Adr 0h should be written as last access with DEBUG_BIT is “0”.
Even “0” write to DEBUG_BIT of EEP_ADR 0h, this write is available but
later access is ignored.
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