MB86613S Datasheet, PDF (2/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
1. Introduction
Related Documents
This specification document was prepared based on the following documents:
1) IEEE1394- 1995 High Performance Serial Bus and P1394a draft2.0
2) 1394 Open Host Controller Interface (Open HCI) Specification Release1.1
3) PCI Local Bus Specification (Revision 2.2)
4) PCI Bus Power Management Specification (Version 1.1)
1.1. Overview
MB86613S is Fujitsu’s IEEE1394- OHCI (Open Host Controller Interface) Controller LSI that is compliant with
IEEE1394- 1995, P1394a and OHCI (revision 1.1, release) standard drafts. This LSI integrates both 1394
PHY and LINK layers including analog PLL, transceiver, and comparator circuits using Fujitsu’s advanced full
CMOS process for the cost- effective single- chip solution.
In addition to the 1394 block, the MB86613S contains various DMA engines called ContextProgram Control-
lers used for OHCI functions and PCI block. ContextProgram block consists of total 13 channels of indepen-
dent DMA that are each dedicated to asynchronous and isochronous transmit and isochronous- asynchro-
nous common receive operations. On- chip, 5V and 3.3V operable, PCI bus controller is compliant with PCI
local bus standard (revision2.2) incorporating one 32- bit DMA controller and power management functions
as specified in PCI bus power management specification (version 1.1).
For valuable host side design, this chip also incorporates serial Configuration ROM interface.
The device operates by +5V or +3.3V power supply for the PCI and DMA blocks and +3.3V for the whole 1394
block.
To provide with the cost- effective solution, the LSI is housed in a 100- pin plastic small QFP package.
1.2. Features
1) 1394 Serial Bus Controller Block:
- Compliant with IEEE1394- 1995 and P1394a draft2.0
- Integrates PHY and LINK layers into single- chip.
- 1394 port number : 1 port
- Transfer Data Rate : S100, S200, and S400
- On- chip PLL : 400MHz for PHY and 50MHz for Link core.
- Cycle- Master Function
- On- chip Bus Management CSRs
- 6- pin cable supported
- On- chip transceiver and comparator
- On- chip another comparator for detecting the cable power
2) ContextProgram Controller Block :
- Compliant with Open HCI standard draft (revision 1.1)
- Total 13 independent ContextProgram Controllers:
a) Asynchronous Transmit DMA : 2 channels for response and request each
b) Isochronous Transmit DMA : 4 channels
c) Receive DMA : 7 channels for Asynchronous response and request each, 4 isochronous,
and 1 self- ID receive
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